Session - 01 - Introduction VLSI Digital Design

PEPs- VSD 514
1 M.S Ramaiah School of Advanced Studies - Bangalore

Session-1
INTRODUCTION
CMOS Digital Design
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Session Objectives
At the end of this session the delegate would have understood
Prominent Driving Trends in Information Service Technologies
Evolution in logic complexity in ICs
VLSI Design Trend
History of VLSI Design
Size & Complexity of IC
Advantages of Integration
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Session Topics
Prominent Driving Trends in Information Service Technologies
VLSI Design Trend
Advantage Integration
What Restricts Further Shrinking of Device Size
COST OF AN INTEGRATED CIRCUIT
A Circuit Design Example

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Prominent Driving Trends in Information Service
Technologies
Portable distributed system architecture
Centralized Information systems architecture
required for network computing and video services.
Need for high processing
power and bandwidth.
Need for intelligent,
portable devices.
Need to integrate in a
small package
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Mobile Services
Voice , short person-to-person messaging including SMS,
MMS, EMS and IM , email
Data networking Microsoft Net Meeting, Customer Relationship
Management (CRM) and Enterprise Resource Planning (ERP) or
Mobile Workforce Management applications
Browsing mobile-specific content (free-to-air information) and
general web access (web browsing)
Entertainment services downloading or accessing games,
cartoons, music, video clips and other forms of entertainment
over a cellular network.
M-commerce transaction-oriented services, e-pay facilities,
mobile shopping portals, mobile banking and share trading, and
bookings and ticketing
Videotelephony real-time, audio-visual, person-to-person
communications.
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Level of integration.
Number of logic gates in a chip.
Fueled by rapid progress in processing technology and
interconnect technology.
Year Complexity#no. of logic blocks per chip
Single transistor 1958 <1
Unit Logic(gate) 1960 1
Multifunction 1962 2-4
Complex Function 1964 5-20
MSI 1967 20-200
LSI 1972 200-2000
VLSI 1978 2000-20000
ULSI 1989 20000-?
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Advantage Integration
Why monolithic integration of a large number of functions on a single chip?
Less die area, more compactness at all system levels
Fewer chips/components per board and system
Less power consumption
Less testing requirements at the system level
Higher reliability, due to improved on chip interconnect
Higher speed, due to reduced interconnect length
Significant cost savings
Demerits of size reduction:
Deterioration in matching characteristics
Increased cost of equipment required for processing the wafers
Additional capability requirements for software design aids
Increased impact of interconnection delays
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Evolution of Minimum Feature Size
Memory chips
VS Logic Chips
Logic chips
contain
significantly
fewer transistor
than Memory
chips as
significant
portion of the
chip area is
consumed by the
complex
interconnects.
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1930-Lilienfield and Heil found FET.
1947/48- Bell Labs Brattin, Bardeen, Schockley BJT 15 years.
1958 Jack kilby first IC
1958 Robert Noyce Procedure for IC Design Today's VLSI
Design
1962 NPN TRANSISTOR
1963 RTL Logic
5 mm
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Germanium was used initially, switched over to silicon 25% of
earths crust is silicon.
Gallium arsenide is gaining acceptance.
IC
Interconnected circuit elements associated with continuous
substrate.
Substrate
Supporting material to fabricate IC
Wafer
Basic physical unit in IC design, circular in shape having
diameter of 4,5 or 6 inches
Chip, Test Plug, Test Cell

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First Point Contact Transistor

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First IC
Simultaneously invented by two different people:
Jack Kilby (TI):
Robert Noyce (Fairchild):
Required wires
Used evaporated aluminum (with Jean Hoerni,a
swiss guy)

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First Commercially Available Integrated Circuit
Developed by Robert Noyce in the
late 1958,
It was a Flip-Flop. Courtesy:
Fairchild Semiconductor.

1962
NPN TRANSISTOR.
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Logic Circuits
1963:
Diode Logic
RTL LOGIC
TTL LOGIC
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MOS circuits
MOS circuits 1967
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Microprocessors
Intel4004 1967
Intel 8008 1972
Pentium PRO1995
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Device count:
number of active devices like FET/BJT on a wafer/die
Feature size:
minimum gate length/minimum polysilicon length/minimum width
Pitch:
minimum width + minimum spacing between same features = 2*minimum
feature size.
Feature size: 7 to 10 microns in 1970 ;
5 microns in early 1980; 1/1.25/2 microns in mid 1980
0.75 - 0.25 microns in 1990; 0.180 micron in 1997
0.130 micron in 2003; 90 nm in 2005 ; 65 nm in 2006
Use dimensions:
1 A = 10
-4
microns = 10
-10
meters = 3.94 X10
-9
inches
1 micron = 104 A = 10
-6
meters = 3.94 X10
-5
inches
1 Mil = 25.4 microns = 2.54 X10
-5
meters = 0.001inches
1 inch = 2.54 X10
-2
meters
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Chip Area Analysis
Number of transistors on a die/chip/wafer (100 mm dia):
W=L=5 microns then, N
5u =
PI* R
2
/ area = 3.14 X 10
8
W=L=0.5 microns then, N.
5u =
PI* R
2
/ area = 3.14 X 10
10
100 fold increase in device count.
Hence, instead of having a single piece of computer fabricated
using 5 micron technology on a single wafer, we can have 100
such computers fabricated on the same wafer with feature size of
0.5 microns.

Other than this, as the transistor size is shrinked, the speed
increases.
Which also increases the yield & complexity.
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What Restricts Further Shrinking of Device Size
Limitations in resolutions of processing equipment
Physics of Semiconductor devices:
Density of silicon atoms is 5 x 10
22
atoms/cm
3
Average distance is 2.71 A, nearest neighbor distance is
1.18A
Density of Silicon di Oxide is 2.3 X 10
22
atoms/cm
3
Average molecular distance is 3.52 A
Quantum Mechanical tunneling occurs if oxide
thickness becomes thinner than 50A, thus placing a practical
restriction on lower bound on oxide thickness.
High electric field strengths:

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What restricts further shrinking of device size
Physics of Semiconductor devices:
High electric field strengths:
E
1000A
= 5V / 1000A = 500kV/cm
Silicon di Oxide breakdown is in the range of 5-10MV/cm.
If we go for 100A then the E
F
is very near to breakdown
voltage.
In order to balance, only option is to reduce the voltage level,
In this case noise effects becomes more significant.
Variations of voltage levels with different manufactures
becomes difficult to interface sub circuits with varying
voltage levels and realize complex circuits.
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COST OF AN INTEGRATED CIRCUIT
FIXED COST: engineering cost, research and development,
indirect costs.

VARIABLE COST: die cost, test cost, package cost
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TYPICAL VLSI DESIGN FLOW
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Design a one-bit binary full-adder circuit using 0.8 mm n-well
CMOS technology. The specifications are:

1. Propagation Delay Times of SUM &
CARRY_OUT signals:
1.2ns
2.

Transition Delay Times of SUM & CARRY_OUT
signals(Rise time and Fall times)
1.2 ns
3. Circuit Die Area: 1500 mm2
4. Dynamic Power Dissipation
(@ VDD = 5 V and fmax = 20 MHz):
1 mW
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Binary full-adder circuit
A three input two output combinational circuit.
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GATE LEVEL SCHEMATIC OF ONE-BIT FULL ADDER CIRCUIT
(use of carry_out to realize sum_out reduces circuit complexity and
chip area)
=AB+(A+B)C
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TRANSISTOR LEVEL SCHEMATIC
Note: 14 NMOS
and 14 PMOS
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Alternate TRANSISTOR LEVEL SCHEMATIC

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Layout
Layout with
W/L =
2mm/0.8 mm
Minimum
size
allowed
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All n-mos and p mos transistors are placed in two parallel rows.
Between the horizontal power supply line and the ground lines.
All poly silicon lines are laid out vertically.
The area between the n type and p type diffusion is used for
running the local metal interconnections.
The diffusion regions of the neighboring transistors are merged as
much as possible to save the chip area.

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Layout
Layout with W/L = 2 mm/0.8 mm
Area 21 mm x 54 mm = 1134 mm
2
< design criteria(1500 mm
2
).
Perform DRC: Check any Physical Design Rule Violations
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Design Verification
Parasitic Extraction: Resistances and capacitances
Use these in tools like SPICE to carry out dynamic analysis.
The parasitic extraction tool
Reads in the Physical layout file
Analyzes the various mask layers to identify transistors,
interconnects and contacts
Calculates the parasitic capacitances and the parasitic
resistances of these structures and finally
Prepares a SPICE input file that accurately describes the
circuit.
Spice simulation

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Simulation
Layout with W/L =
2 mm/0.8 mm
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Simulation Results
Desired:
1.Propagation Delay Times of SUM & CARRY_OUT signals:
1.2ns
2. Transition Delay Times of SUM & CARRY_OUT signals: 1.2
ns
3. Circuit Die Area: 1500 mm2
4. Dynamic Power Dissipation
(@ VDD = 5 V and fmax = 20 MHz): 1 mW

Obtained:
1.Worst Case Delay : 2ns
3. Circuit Die Area: 1134 mm2.
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Layout Modification
Modified Layout Required
An iterative Process
1. Layout Modification
2. Parameter Extraction
3. Simulation
Increase W/L's of transistors
Consider more compact placement of transistors and reduce interconnect in
critical paths eg; Carry_OUT
Rearrange the transistors to reduce the area and to reduce interconnection
parasitics.

Final Results: Area: 43X90 mm
2
=1290 mm
2
Propagation Delay : 1.0ns
Dynamic Power Dissipation = 460 mW

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The full adder can be used to design more complex circuit eg
An 8 bit binary adder.
Can be arranged in Cascade: Carry ripple adder
Arranging input and output bus
Used in ALU and DSP circuits
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Issues
CMOS digital integrated circuits involves a wide range of issues:
Boolean Logic
Gate level Design
Transistor Level Design
Physical Layout Design
Parasitic Extraction
Circuit Simulation
Design Tuning
Performance Verification
The design is iteratively simulated until it meets the desired
specification with sufficient margins.

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TYPICAL VLSI DESIGN FLOW
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VLSI Design Methodology
Overall Design Flow
Important Design Concepts
VLSI Design Styles
Quality Of Design
CAD Technology
Classification of CMOS Digital Circuits.
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VLSI Design Methodology
IMPACT OF DIFFERENT VLSI DESIGN STYLES ON DESIGN CYCLE
TIME AND ACHIEVABLE CHIP PERFORMANCE
Choice of the style depend on:
Performance Requirements
Technology
Expected life time of the product
Cost of the project.
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VLSI DESIGN FLOW
3 DOMAIN
REPRESENTATIONS
Algorithms
Processor
Module Placement
Finite State
Machines
Functional Modules:
Register ALU
Chip Floor Plan
Module Description
Cell Placement
Leaf Cell :Logic gates
Mask
Boolean Equations
Transisters
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VLSI DESIGN FLOW
3 DOMAIN REPRESENTATIONS
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GOAL OF MODERN DESIGN SYSTEMS
Convert spec at HIGHEST LEVEL possible into a SOC design in
MINIMUM TIME and with MAXIMUM LIKLIHOOD that the
design will PERFORM AS DESIRED when fabricated.

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SIMPLIFIED VLSI DESIGN FLOW VIEW IN THREE DOMAINS
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OBJECTIVE: transfer design description in behavioral domain into
a
fully equivalent design descriptions in the other domains.
-> Guiding Design Organization Principles
-> Design Options Avialable to CMOS IC Designers

Fast
Prototyping
Low Volume
Custom Design
Labor Intensive
High Volume
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Design Strategies
Design Parameters By Which Design Success Is Measured:
Performance Specs - function, timing, speed, power
Size of Die - manufacturing cost
Time to Design - engineering cost and schedule
Ease of Test Generation & Testability - engineering cost, manufacturing
cost, schedule
Design is a continuous tradeoff to achieve performance specs with adequate results in
all the other parameters.
Structured Design Strategies
Strategies common for complex hardare and software projects.
Hierarchy: Subdivide the design into several levels of sub-modules
Modularity: Define sub-modules unambiguously & well defined
interfaces
Regularity: Subdivide to max number of similar sub-modules at each
level
Locality: Max local connections, keeping critical paths within module
boundaries
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MODULARITY
ADDS TO HIERARCHY AND REGULARITY THE
QUALITIES OF
WELL DEFINED FUNCTIONS AND INTERFACES
-> Unambiguous functions
-> Well defined behavioral, structural, and physical interfaces
-> Enables modules to be individually designed and evaluated.

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CIRCUIT AND SYSTEM REPRESENTATIONS
COMPLEX DIGITAL SYSTEM can be SUCCESSIVELY SUB-
DIVIDED in a HIERARCHIAL manner.
Highly automated techniques exist for converting HIGH
LEVEL DESCRIPTIONS OF SYSTEM
BEHVIOR to a detailed implementation prescription to
fabricate a CHIP.
To do this, a set of ABSTRACTIONS have been developed to
describe integrated electronic systems.
Designs are represented in THREE distinct DOMAINS:
1. Behavioral: what does the system do?
2. Structural: how are the elements connected together?
3. Physical: how is the structure to be built?

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CIRCUIT AND SYSTEM REPRESENTATIONS
Each DESIGN DOMAIN can be specified at a
variety of LEVELS of ABSTRACTION
- Architectural
- Algorithmic
- Module or Functional Block
- Logical
- Switch
- Circuit

Higher Level
Lower Level
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FLOORPLANNING
MAINTAIN IDENTICAL HIERACHIES IN BEHAVIORAL, STRUCTURAL
AND
PHYSICAL DOMAINS
Mapping Structural
Hierarchy into
Physical Hierarchy
FLOORPLANNING
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REGULARITY
DESIGN THE CHIP HIERARCHY INTO IDENTICAL OR
SIMILAR MODULES
EXTENDED USE OF REGULARITY SIMPLIFIES THE
DESIGN PROCESS
REGULARITY CAN EXIST AT ALL LEVELS OF DESIGN
HIERARCHY
Circuit Level: uniform transistor sizes rather than manually
optimizing each device.
Logic Level: identical gate structures rather than customize
every gate.
Architecure Level: construct architecures that use a number of
identical processor structures

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LOCALITY
TIME LOCALITY: modules see a common clock and
synchronous timing is applied.
Robust clock generation and distribution is critical
Critical paths, where possible, are to be kept within module
boundaries
Any global module to module signal should have an entire
clock cycle to traverse the chip.
Replicate logic, if necessary, to alleviate cross-chip crossings.
Locate modules in layout to minimize large or "global" routes
between modules.

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TYPICAL DESIGN ABSTRACTIONS IN DIGITAL VLSI DESIGN

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TOP LEVEL DIAGRAM OF A RASTER GRAPHICS VECTOR
GENERATOR

STRUCTURAL HIERARCHY
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PHYSICAL MODULARITY FOR DIFFERENCE ENGINE BASED ON 8
IDENTICAL BIT SLICES

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CMOS Chip design options
Programmable Logic - mP, DSP
Programmable Logic Structures -
FPGA
Programmable Interconnect - FPGA
Mask Progmmable Gate Arrays
Standard Cell Design
Mixed Standard Cell & Custom Design
Full Custom Mask Design

Design
Investment
Increasing
(for a
given
application)
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STANDARD-CELLS (POLYCELL) BASED DESIGN
Predominant full-custom design style.
Standardization is achieved at the logic or function level.
Specific designs for each gate can developed and stored in a software database
or cell library.
Behavioral, Structural, and Physical Domain descriptions per cell
Layout is usually automatically placed and routed using CAD software.
Typical Standard Cell Library contents:
SSI logic: e.g. nand, nor, xor, inverters, buffers, latches, registers
Each gate can have multiple implementations to provide proper drive for
different fan-outs, e.g. standard size, 2x, 4x
MSI logic: e.g. decoders, encoders, adders, comparators
Datapath: e.g. ALUs, adders, register files, shifters
Memories: e.g. RAM, ROM
System level blocks: e.g. multipliers, microcontrollers

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SSI/LSI blocks: layout style is rows of constant hight blocks
separated by rows of routing.
SSI/LSI standard cell concept is extended to higher level
functions, often available as parameterized modules.

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Standard Cell Based Design
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Field Programmable Gate Array
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METAL MASK DESIGN FOR DOUBLE BUFFER
ON MASK PROGRAMMABLE GATE ARRAY
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FULL CUSTOM DESIGN
GATE MATRIX LAYOUT STYLE
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Design Quality
DESIGN QUALITY
ACHIEVE SPECIFICATIONS (Static & Dynamic)
DIE SIZE
POWER DISSIPATION

TESTABILITY
YIELD AND MANUFACTURABILITY
RELIABILITY

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Design Quality
TESTABILITY
generation of good test vectors
availablity of reliable test fixture at speed
design of testable chip
YIELD AND MANUFACTURABILITY
functional yield
parametric yield
RELIABILITY
premature aging (Infant mortality)
ESD/EOS
latchup
on-chip noise and crosstalk
power and ground bouncing
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PACKAGING TECHNOLGY
INCLUDE IMPORTANT PACKAGE RELATED PARASITICS IN THE
CHIP DESIGN AND SIMULATION <-
Package Power & Ground Planes -> on-chip power and ground busses
Bond Wire Lengths -> on-chip inductive effects
Thermal Resistance -> temp rise due to on-chip power dissipation
Package Cost
IMPORTANT PACAKGE DESIGN CONCERNS:
Hermetic seals to prevent penetration of moisture
Thermal conductivity
Thermal expansion coefficient
Pin density
Parasitic inductance and capacitance
A-paricle protection (memories)

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PACKAGE TYPES
DUAL IN-LINE PACKAGE (DIP):
1. Ceramic or plastic pin-through-hole (PTH)
2. Low cost, but large size
3. High lead inductance (22 - 36 nh)
4. Max pin count usually 64
Pin grid array (PGA) package
1. Ceramic or plastic pin-through-hole (PTH)
2. Higher pin count (100 - 400 pins)
3. Larger PCB area and higher cost than DIP
Chip carrier package (CCP)
1. Surface-mounted technology (SMT)
2. Leadless chip carrier supports high pin count
3. More efficient use of PCB area than DIP or PGA
4. Flip chip or ball grid array technogy for higher density
Multi-chip module (MCM)
1. Multiple chips assembled on a common substrate
2. High performance applications
3. Most efficient use of PCB area
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VLSI CAD Technology
CATAGORIES OF CAD TOOLS
1. High level synthesis (hdls)
2. Logic synthesis
3. Circuit optimization
A. Transistor sizing for min delays
B. Process variations
C. Statistical design
4. Layout
A. Floorplanning
B. Place & route
C. Module generation
D. Automatic cell placement and routing
5. Layout extraction
6. Simulation (SPICE for circuit-level simulation)
7. Layout - schematic verification
8. Design rule check
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Design of VLSI Circuits
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Classification of Digital Circuit Types

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MOS TRANSISTORS
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MOS TRANSISTORS
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nMOS and pMOS SWITCH SYMBOLS AND
IDEAL CHARACTERISTICS
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OUTPUT LOGIC LEVELS OF
N- AND P- SWITCHES

OUTPUT
LEVEL
SYMBOL SWITCH CONDITION
Strong 1 1 P-SWITCH gate = 0, input = VDD
Weak 1 1

N-SWITCH gate = 1, input = VDD
Strong 0 Weak 0 0 N-SWITCH gate = 1, input = VSS
0 P-SWITCH gate = 0, input = VSS
High Impedance Z N-SWITCH gate = 0 or
P-SWITCH gate = 1

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COMPLEMENTARY CMOS SWITCH
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INVERTER TRUTH TABLE
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INVERTER Design
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CONNECTION & BEHAVIOR OF SERIES N- AND P- SWITCHES
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CONNECTION & BEHAVIOR OF PARALLEL N- AND P- SWITCHES
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2-INPUT CMOS NAND GATE
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2-INPUT CMOS NOR GATE
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COMPOUND GATES
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2-INPUT MULTIPLEXER
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SUMMARY
Day by Day the complexity of the VLSI circuit is increasing.
As a result the CAD tools also have become very complex.
It has become necessary to divide the expertise in four domains
The system level modelling
The Logic level modelling
The gate level modelling
The physical level modelling
Optimization at each level has become essential and requires
complex modelling and simulation tools.

Session - 01 - Introduction VLSI Digital Design

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1 M.S Ramaiah School of Advanced Studies - Bangalore

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