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A d d re s s B u s 2 0 b its
AH AL S U M M A T IO N
BH BL
D a ta B u s
CH CL
CS
DH DL
DS
SP
SS
BP
ES
DI
IO
BI
In te rn a l Bus
C o m m u n ic a tio n s C o n tr o l
R e g is te rs
8088
Bus
T e m p o r a ry
R e g is te rs
In s tru c tio n Q u e u e
ALU
EU
C o n tr o l
1 2 3 4
F la g s
• 8086/8088 consists of two internal units
– The execution unit (EU) - executes the instructions
– The bus interface unit (BIU) - fetches instructions,
reads operands and writes results
• The 8086 has a 6B prefetch queue
• The 8088 has a 4B prefetch queue
BIU Elements
• Instruction Queue: the next instructions or data can be
fetched from memory while the processor is executing
the current instruction
– The memory interface is slower than the processor
execution time so this speeds up overall performance
• Segment Registers:
– CS, DS, SS and ES are 16b registers
– Used with the 16b Base registers to generate the 20b
address
– Allow the 8086/8088 to address 1MB of memory
– Changed under program control to point to different
segments as a program executes
• Instruction Pointer (IP) contains the Offset Address of
the next instruction, the distance in bytes from the
address given by the current CS register
EU Elements
• Internal Registers
23 QS1 and QS0 : The queue status bits show status of internal
instruction queue. Provided for access by the
numeric coprocessor (8087).
S2, S1, S0 : Indicate function of current bus cycle (decoded by 8288).
8284A Clock Generator
Single 18 pin chip Clock Generator for 8086and 8088
Basic functions:
• Clock generation.
• RESET synchronization.
• READY synchronization.
• Peripheral clock signal.
Pin Functions
1 AEN1 &AEN2 Address enable pins to qualify the bus ready signal, RDY1 & RDY2
2 RDY1 & RDy The bus ready provided in conjunction with the AEN1 & AEN2 pins to cause
wait
3 ASYNC Ready synchronization selection input selects either 1 or 2 stages of
synchronization
4 READY It is an output pin connected to 8086/8088.
5 X1 & X2 Crystal oscillator pins connect to an external crystal used as timing source
8 CLK The clock output pin provides the CLK input signal to 8086/8088. It is one
third of the Crystal or EFI signal
10 OSC Oscillator output-same frequency as the crystal or EFI, it provides the EFI
input to other 8284A.
11 RES The reset input is connected to an RC network that provides power-
on resetting
12 RESET The reset output connected to 8086/8088 RESET input pin.
Top half of the logic dig. Represents the clock and reset synchronization.
Clock section
• If a crystal is attached to X1 & X2 The Oscillator generates a square wave
signal at the same frequency as the Crystal.
• This signal is fed to OSC out put through an inverting buffer. This o/p can be
connected to the EFI of another 8284A.
• The AND gate circuit is used to select EFI or the Oscillator generated wave
with the help of F/C input.