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Radiation Effects Challenges in 90nm

Commercial-Density SRAMs:
A Comprehensive SEE and TID Study
Jeff Draper, Y. Boulghassoul, M. Bajura, R. Naseer, J. Sondeen and S. Stansberry
University of Southern California
Information Sciences Institute

1st Workshop on Fault-Tolerant Spaceborne Computing Employing New Technologies


CSRI, Sandia National Labs, Albuquerque, NM
May 28-30, 2008

This work was supported by the Defense Advanced Research Projects Agency (DARPA)
Microsystems Technology Office under award No. N66001-04-1-8914
Any opinions, findings, and conclusions or recommendations expressed in this presentation are those of the authors
and do not necessarily reflect the views of DARPA/MTO or the U.S. Government
Motivations

• RHBD approach shown to be effective for 90nm designs,


within acceptable “1 process generation” penalty
• Use of RHBD for SRAMs poses bigger challenges
 SRAM density achieved through aggressive design rule waivers
 Cell-level radiation hardening using typical RHBD techniques
compounds area/speed/power penalties

• Traditional circuit-based RHBD approach


 Hardens control structures and individual memory cells
 SRAM BER largely determined by the raw BER of the memory cell

• Objective: Investigate best rad-hard SRAM performance


achievable through hybrid hardening approach
 Harden control structures but leave commercial SRAM cell density
and technological scaling of individual memory cells intact
 Mitigate SEUs (SBU/MBU) with device-centric ECCs
 Leverage intrinsic process hardness for improved reliability
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Outline

• SRAM test chips overview


• SEU response
 Heavy-Ions
 Protons

• Latchup response

• TID and temperature annealing


 24C, 100C and 150C

• Summary and conclusions

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Overview SRAM Test Chips
DESIGN COMMERCIAL “AS MODIFIED FOR SPACE
ATTRIBUTE IS” - BASELINE OPERATIONS –
HARDENED
IBM PROCESS 9LP
Size (Total Bits) 65, 536 90, 112
Voltage (V) Core: 1.2 V; I/O; 2.5 Core: 1.2 V; I/O; 2.5
I/O Pads Radiation-Hardened Radiation-Hardened
Design Libraries: Phase-1 (RHBD) Phase-1 (RHBD)
Error Correction None 1 bit (Hamming; 22, 16, 4)
Area Overhead 1X 1.37X
IBM PROCESS 9SF
Size (Total Bits) 57,344 122,880
Voltage (V) Core: 1.0 V; I/O; 2.5 Core: 1.0 V; I/O; 2.5
I/O Pads Commercial (Artisan) Commercial (Artisan)
Design Libraries: Commercial (Artisan) Commercial (Artisan)
Error Correction None 2 bits (BCH; 15,7,5)
Area Overhead 1X 2.14X

• Fabricated 4 SRAMs in 9LP and 9SF processes (1 baseline, 1 hardened in each)


• Key design objectives: Use commercial core memory cells (FP118 and E123)
 Harden peripheral circuitry using TMR, annular gates, interleaving
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RHBD SRAM
Approach/Design
Block SET Hardening

Bit Interleaving (MBU Mitigation)


Decoders, ECC, Timing #1

Decoders, ECC, Timing #2

Decoders, ECC, Timing #3

0 1 2 3 0 1 2 3 0 1 2 3
Voter

0 1 2 3 0 1 2 3 0 1 2 3
0 1 2 3 0 1 2 3 0 1 2 3

0 0 0 1 1 1 2 2 2 3 3 3
0 0 0 1 1 1 2 2 2 3 3 3
TMR 0 0 0 1 1 1 2 2 2 3 3 3

Cell TID & SEL Hardening


Array SEU Hardening (SEC/DED)

Annular gates
(TID)

Guard rings 5
(SEL)
- Single Event Effects -
SEU

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SEU Raw Cross Sections
HI Test Results
BASELINE

LP SF
HARDENED

LP SF

Memory Patterns={00,11,10}, Static/Dynamic = {s, d}; LP Dynamic Access Rate 2.2 KHz per bit; SF Dynamic Access Rate 718 Hz
Data collected at LBNL 88” Cyclotron, 10 MeV cocktail, core voltage 10% below nominal, 100 MHz tester. Fluence range 1e7-1e5. #Errors>256 ea. pt.
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SEU Cross Section Calculations
Pre-ECC and Scrubbing

s
• Weibull(x) = [ a ]*[ 1-e{ ((x-x0)/w)) } ]
• SF cross-section ~ 2-3 X higher than
LP, likely due to lower Vdd
• No cross-section dependence on
static vs. dynamic testing
• Minor differences between baseline
and hardened suggest little impact of
TMR control circuitry

Raw Upsets / Bit-Day Before ECC and Scrubbing


Weibull Cross-Section Parameters (per bit) Geo. Orbit
Device Eq. Orbit
Configuration 3,000 km
Solar Flares
a X0 w s Max GCR Min GCR (Rad. Belts)
Worst Week

sfb 3.3e-8 .30 23 1.3 2.3e-7 7.2e-8 1.4e-4 2.4e-4


sfh 3.3e-8 .43 28 1.2 2.0e-7 6.2e-8 8.6e-5 1.1e-4
lpb 1.8e-8 .73 36 .91 1.2e-7 3.8e-8 2.4e-5 2.0e-6
lph 1.8e-8 .40 34 1.1 1.1e-7 3.3e-8 3.7e-5 3.8e-5
Calculations using CREME96, 100 mil shielding. AP8 model for equatorial orbit.

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SEU Model
ECC and Scrubbing *
P(error) per scrub vs. ECC and Scrub Rate BER reduction vs. ECC and Scrub Rate

2
1

1. P(error) depends on the ratio of the device’s


Constant 1E-10 BER curves vs. ECC and Scrub Rate
memory array SCRUB RATE and its RAW BER,
and ECC applied
2. Overall reduction in error-rate is relative to
starting physical raw BER.
 Example: Scrub rate=100, Physical
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BER=10-6, Single-bit ECC, improves BER
by 10-4 – New Effective BER 10-10
3. Goal: Assume once/10 seconds scrub rate and
10-10 BER; the device can tolerate up to 10-5
errors/bit-day with single-bit ECC, 10-2
errors/bit-day with double-bit ECC.
*. Figures assuming 22-bit code from “Models and Algorithmic Limits for an ECC-Based 9
Approach to Hardening Sub-100nm SRAMs”, IEEE TNS Vol. 54, pp. 935-945, Aug. 2007.
Comparison of ECC Model with
SEU Experimental Data

LPH STATIC SFH STATIC LPH DYNAMIC SFH DYNAMIC

Scrub Rate /bit 1 / Run 2.22 kHz 0.718 kHz

Errors / Run / Time (Secs) / Memory


Raw BER Errors / Run / Memory Size
Size

Effective BER Equation A Equation B Equation A Equation B

Total SBUS (All SEU Runs) 13,004 12,117 9,901* 9,372

Total Bit Errors Observed (Not


7,305 195 NO ERRORS NO ERRORS
Corrected by ECC)
Total Bit Errors Predicted by
the Model for a Given Scrub 7,633 187 6.7 (< 1 word) 0.0002
Rate, Raw BER and ECC

Approximate Effective BER Raw BER


Equation A ~ Raw BER
Equations for Single-bit- Equation B ~
correcting 22-bit word and (1-bitt ECC) Scrub Rate/Raw BER (2-bitt ECC) 2
Scrub Rate/Raw BER
1+ 1+
Double-bit-correcting 15-bit word 300 15

• Distribution of observed errors from measurements matches the ECC model very
well
 Proper error correction code (ECC) and modest scrubbing rate combination
ensures a BER better than 10-10 errors/bit-day in all orbital scenarios 10
SBU and MBU analysis vs.
Effective LET
Single and Multi Bit Upset Distributions vs. Effective LET for LP and SF SRAMs

9LP

9SF

• Large differences in the SBU/MBU distribution between LP and SF SRAMs


for similar LET values
 Particularly noticeable for LET> ~10 (MeV-cm2/mg)
• Saturating cross-sections have LET-dependent error distributions
 LET of 31 and 117 have comparable cross-sections but different distributions
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SEU Proton Testing

• IBM 90nm commercial density SRAM cells have a very low upset threshold
 From 3D TCAD simulations, worst-case Qcrit ~1.1fC

• With an SRAM cell threshold LET < 0.5 MeV.cm2/mg, protons could
potentially become capable of inducing SEUs through direct ionization
 Possible drastic increase in raw memory cell BER
 Could flood 1bit and possibly even 2 bit ECC schemes

SRAM type Bit configurations Average cross-section/bit.cm 2

9LP Baseline All 0, All 1, 10 2.99E-14

9LP Hardened All 0, All 1, 10 2.84E-14

9SF Baseline All 0, All 1 5.92E-14

9SF Hardened All 0, All 1 7.24E-14


Data collected at Indiana University cyclotron facility, 200Mev line. Proton flux ~ 1010particles/cm2.s. Max TID for each tested part ~ 20Krad.

• SRAM saturating cross-section still well behaved for worst-case 200Mev


proton exposure (~ 10-14 errors/bit.cm2)
 Proton upsets Saturating
from nuclear interactions,
cross-section no for
of 9SF and 9LP SRAMs direct ionization
a 200MeV yet @ 90nm
proton exposure.

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- Single Event Effects -
Latchup

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Latchup in 90nm SRAMs

Device
Experimental
LP BASELINE LP HARDENED SF BASELINE SF HARDENED
Condition

High V Vcore = 110% 1.32 V 1.1 V


High Heat Temp = High 125 C 125 C
(worst case) LET Threshold Between 0.87 and 2.22 > 117
Vcore = 110% 1.32 V
High V
Temp = Room ~ 24 C
No Heat
LET Threshold > 117
Not applicable
Latch Up Vcore Between 1.10 - 1.14 V
Onset and
Temp = High 125 C
Release
Data collected atLET
Voltages > 117through RTD strapped to PGA package and PID control
LBNL 88” Cyclotron, 10MeV cocktail. High T applied

• SF appears to be SEL immune


• LP appears to be SEL immune if, and only if:
– At room temperature over voltages up to 110% Vcore, OR
– At lowered voltage over temperatures up to 125 C
• All SELs observed in LP were non-destructive
• LP latchup appeared as a single step-function of ~50 mA
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- Total ionizing Dose -
9LP/9SF TID and Room T0
Annealing Responses
• TID-induced Core leakage currents of Baseline and Hardened SRAMs were
identical for a given process
 TID response of SRAM Core is dominated by memory array leakage

9LP and 9SF SRAM Core leakage currents dynamics as a function of TID and 24C anneal
1.E-06 1.E-06
Leakage Current / Bit (A)

Leakage Current / Bit (A)


1.E-07 1.E-07

1.E-08 1.E-08

1.E-09 9LP Core @ 1.2V 9LP Core @ 1.2V


1.E-09
9SF Core @ 1V 9SF Core @ 1V

1.E-10 1.E-10
0 500 1000 1500 2000 1 10 100 1000
Cummulated Dose (krads) Annealing Time @ 24C (days)

9LP SRAM: 9SF SRAM:


- ~ 1000X increase in Core leakage current @ 2Mrad - ~ 50X increase in Core Leakage current @ 2Mrad
- 4/4 devices functional failure [1000 <X<1300] - 20X pre-rad leakage but same level as LP @
krads 2Mrad
- 4/4 devices fully functional after 7 days annealing - 4/4 devices functional failure [600<X<1000] krads
- Leakage ~ 30X after 140 days - 2/4 devices fully functional after 7 days annealing
All devices irradiated @ 200 rads/sec, Max Temp -< Leakage ~ 8X
30 C, removed after 140
~15 minutes days
for measurement
LP irradiated under 10 pattern & measured under 01; SF irradiated under 00 pattern & measured under 11 16
9LP/9SF TID and Room T0
Annealing Responses (cont.)
• TID-induced IO leakage currents showed drastic differences between
hardened and unhardened IO pads
 Hardened pads should be used whenever possible
 Major impact on reliability at negligible performance penalties

9LP and 9SF SRAM IO leakage currents dynamics as a function of TID and 24C anneal
1.E-01
1.E-01

1.E-02
Leakage Current (A)

1.E-02

Leakage Current (A)


1.E-03 1.E-03

1.E-04 1.E-04

9LP IO @ 2.5V 9LP IO @ 2.5V


1.E-05 1.E-05
9SF IO @ 2.5V 9SF IO @ 2.5V

1.E-06
1.E-06
1 10 100 1000
0 500 1000 1500 2000
Annealing Time @ 24C (days)
Cummulated Dose (krads)

9LP SRAM: 9SF SRAM:


- Hardened IO pads (MRC design) - Unhardened IO pads (Artisan cells)
- ~ 1A IO leakage up to 2Mrad - ~ 104 X increase in IO leakage @ 2Mrad
- Leakage ~ 2000X after 140 days

All devices irradiated @ 200 rads/sec, Max Temp < 30 C, removed ~15 minutes for measurement
LP irradiated under 10 pattern & measured under 01; SF irradiated under 00 pattern & measured under 11 17
9LP/9SF TID Responses for
100C and 150C anneals
• All 9LP and 9SF SRAMs respond very well to a temperature annealing
 For 100C, Core leakage currents are within 3X of pre-rad < 100 hours
 For 150C, pre-rad Core leakage levels are reached within 5 hours

9LP and 9SF SRAM Core leakage current variation as a function of annealing temperature

1.E-06 1.E-06
Leakage Current / Bit (A)

Leakage Current / Bit (A)


9LP Core @ 100C 9SF Core @ 100C
1.E-07 1.E-07
9LP Core @ 150C 9SF Core @ 150C

1.E-08 1.E-08

1.E-09 1.E-09

1.E-10 1.E-10
0 50 100 150 0 20 40 60 80 100
Annealing Time (hours) Annealing Time (hours)

• The unhardened IO did not respond well


 100C anneal is ineffective: still ~ 1000X above pre-rad after 200 hours
 150C anneal is slightly better with 10X above pre-rad after 60 hours

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TID Radiation Hysteresis

• Successive TID exposure and annealing cycles induced a shift in


the SRAM leakage characteristics:
 Lateral shift: the SRAM start degrading sooner than in its first irradiation
 Vertical shift: the current “saturation” level is lowered
 But the true mystery improvement to the SRAM reliability is…

1.E-06 1.E-06

Leakage Current / Bit (A)


Leakage Current / Bit (A)

1.E-07 1.E-07

1.E-08
1.E-08
9LP Core @ 1.2V
9LP Core after 58h@180C 9SF Core @ 1V
1.E-09
1.E-09 9SF Core after 58h@180C
9LP 2nd TID exposure
9SF 2nd TID exposure
1.E-10
1.E-10 0 500 1000 1500 2000
0 500 1000 1500 2000
Cummulated Dose (krads)
Cummulated Dose (krads)

All SRAMs re-exposed a second time NEVER exhibited


functional failure up to 2Mrad
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Summary and Conclusions

• Single Event Upsets (SEU) and Bit-Error-Rate (BER)


– Proper ECC strength, bit interleaving and modest scrubbing rate combination ensures
an SRAM BER better than 10-10 errors/bit-day in all space environments investigated.
• Single Event Latch-up (SEL)
– 9SF commercial memory cells are latch-up immune.
– 9LP commercial memory cells are latch-up free only under high temperature or high
voltage, but not both.
– Voltage scaling is likely to mitigate SEL concerns for core voltages < 1.1V.
• Total Ionizing Dose (TID)
– 90nm SRAMs showed to be intrinsically resilient up to 300krad, but a substantial static
leakage increase happens past 500krad (10X).
– TID Hardened IO pads should be used whenever possible.
– 9LP/9SF SRAMs are very responsive to temperature treatments:
 All SRAMs regained pre-rad nominal currents within 5 hours of 150°C annealing
after 2Mrad TID exposure.
 All ICs recovered from catastrophic loss of functionality.
– Successive exposure and annealing cycles induced hysteresis in the SRAM leakage
characteristics:
 The current degradation starts earlier
 However, the maximum leakage at 2Mrad is lower than for the first irradiation.
– All ICs that underwent complete thermal anneal NEVER exhibited functional failure up
to 2Mrad when re-exposed.
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