DEEP-SUBMICRON

MICROPROCESSOR DESIGN
ISSUES

By
SURYA MOL T
No:18

I ntroduction
Deep-submicron technology allows billions of
transistors on a single die, potentially running at
gigahertz frequencies
According to SIA projections, the number of
transistors per chip and the local clock frequencies
for high-performance microprocessors will continue
to grow exponentially
Ensures future microprocessors will become ever
more complex

I SSUES
Reliability
Hard errors

Soft errors
Hard Errors
Electromigration
Self heating
Hot carriers
Over voltage Failure
Circuit Pitfalls
Electromigration

current densities and power are consequently high

electron movement induced by the current causes
metal ions to migrate

two types of electromigration

Self Heating
High current dissipate power in the wire which raises
its ambient temperature

Hot wires exhibit greater resistance and delay

Bidirectional wires self heating may cause
temperature induced electromigration problems


Hot Carriers
As transistor switches hot carriers may inject into the
gate oxide and get trapped

Changes IV characteristics

Circuit gets wear out
Overvoltage Failure
Problems arise from

Electrostatic discharge
Oxide breakdown
Punch through
Time dependent dielectric breakdown
Circuit Pitfalls
Includes
Threshold drop ,Coupling Charge Sharing ,Ratio
failures, Minority carrier concentration, race
conditions, Hot spots, Back gate coupling, Delay
matching ,Soft errors, Process Sensitivity, Diffusion
input noise sensitivity ,Power supply
noise,metastability

Soft Errors
Random non recurring single bit errors in memory
devices

Minimized by maintaining at least critical charge
TECHNOLOGY
Lightly Doped Drain
To reduce the hot electron effects

Parasitic capacitance is suppressed

Intensity of electric field in drain is decreased

Reduction of high electric potential drops in
drain region

Reduce Device Reliability
Silicon on insulator

Use of a layered silicon-insulator-silicon substrate in place of
conventional silicon substrates

To reduce parasitic device capacitance, thereby improving
performance

SOI wafers can be produced by methods such as

SIMOX
Wafer Bonding (NanoCleave,Smart cut Process,
ELTRAN)


CONCLUSI ON
In the deep-submicron era, greater capacity
(computational as well as memory) and faster
transistors encourage exploration of new
architectural domains and execution paradigms

THANK YOU