1

Dynamic CMOS Logic

2
Dynamic Circuits
Domino Logic
Dual-rail Domino Logic
Keepers
Multiple-output Domino Logic (MODL)
NP Domino Logic

3
Logic function is implemented by the PDN only
No. of transistors is N+2
Smaller in area than static CMOS
Full swing outputs (V
OL
= gnd and V
OH
= V
DD
)
Non-ratioed
Faster switching speed
Power dissipation should be better
Needs precharge clock.
Dynamic CMOS Logic
4
Dynamic CMOS Precharge-Evaluate Logic
Reduced Transistor Count
=0 C
precharges to
V
DD
(output is
not available
during precharge)
=1 C
selectively
discharges to 0
(output is only
available after
discharge is
complete)

V
DD
nMOS
Logic
inputs

C

V
out
M
e
M
p
Internal
capacitance

t

t

V
out
precharge precharge
evaluate
5
Dynamic CMOS Precharge-Evaluate Logic
An Example

V
DD
V
out
M
e
M
p
A
1
A
2
A
3
B
1
B
2
V
out
is high when =0
V
out
=(A
1
A
2
A
3
+B
1
B
2
)
6
Dynamic CMOS Precharge-Evaluate Logic
Cascading Problem
Evaluate:
M
e1
, M
e2
ON
M
p1
, M
e2
OFF
Problem: All stages must evaluate simultaneously one
clock does not permit pipelining of stages.

V
DD
nMOS
Logic
V
out1
1st stage
1

V
out2
V
DD
2nd
V
out1
does not switch from
t

t

V
out
t

V
out
correct state
erroneous state
precharge evaluate
1 to 0 fast enough inputs

M
e1
M
e2
M
p1
M
p2
7
High Performance Dynamic CMOS Circuits
Domino CMOS Logic

V
DD
nMOS
Logic
V
out
V
DD
inputs

X

precharge evaluate
1

t

Static inverter serves to buffer the
logic part of the circuit from its
output load
=0
X precharges to V
DD
, and V
out
=0.
=1
X remains high, and V
out
remains
low.
X discharges to 0, and V
out

changes from 0 to 1.
8
Domino CMOS Logic

V
DD
nMOS
Logic
inputs

V
DD
nMOS
Logic
X
1
V
DD
nMOS
Logic
X
2 X
3
t

t

X
1
t

precharge
evaluate
t

X
2
X
3

evaluate
t
eval
Max number gates limited:
total propagation delay <t
eval
9
Domino CMOS Logic (Cont.)
The problem in cascading conventional dynamic CMOS occurs
when one or more inputs make a 1 to 0 transition during
evaluation.
Domino circuits can fix the above problem
During the evaluation, each buffer output can make at
most one transition (from 0 to 1), and thus each input
of all subsequent logic stages can also make at most one
(0 to 1) transition.
X
3

V
DD
nMOS
Logic
inputs

V
DD
nMOS
Logic
X
1
V
DD
nMOS
Logic
X
2
10
Domino CMOS Logic The Limitations
The static CMOS and domino gates can be used together.
The limitation: the number of inverting static logic
stages in cascade must be even, to let the inputs of next
domino stage can have only 0 to 1 transitions during the
evaluation.
Can implement only non-inverting logic .
Due to precharge use, can suffer from charge
sharing during the evaluation which may cause
erroneous outputs.
The problem will be described in the next slide, and
several solutions will be presented later.

11
Domino CMOS Logic - Charge Sharing
Assume that all inputs are low initially, and the
voltage across C
2
=0V
During the precharge, C
1
is charged to V
DD
If transistor N switches from 0 to 1 during the
evaluation phase, the charge initially stored in C
1

will be shared by C
2
. Therefore, the value of V
X
will
reduced.

V
DD
V
out
V
DD
V
X
C
1
C
2
V
X
=V
DD
C
1
/(C
1
+C
2
)
Keep C
2
<<C
1
N

12
Domino CMOS Logic
Reduce Charge Sharing Degradation of V
X

V
DD
nMOS
Logic
inputs

V
out
V
X
Push V
X
to V
DD
unless there
is a strong pull-down path
between V
out
and ground
weak pull-up pMOS
9: Circuit Families Slide 13
Dual-Rail Domino
Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR
Dual-rail domino solves this problem
Takes true and complementary inputs
Produces true and complementary outputs
sig_h sig_l Meaning
0 0 Precharged
0 1 0
1 0 1
1 1 invalid
Y_h
f

inputs
Y_l
f
9: Circuit Families Slide 14
Example: AND/NAND
Given A_h, A_l, B_h, B_l
Compute Y_h = A * B, Y_l = ~(A * B)
9: Circuit Families Slide 15
Example: AND/NAND
Given A_h, A_l, B_h, B_l
Compute Y_h = A * B, Y_l = ~(A * B)
Pulldown networks are conduction complements
Y_h

Y_l
A_h
B_h B_l A_l
= A*B
= A*B
9: Circuit Families Slide 16
Example: XOR/XNOR
Sometimes possible to share transistors
Y_h

Y_l
A_l
B_h
= A xor B
B_l
A_h A_l A_h
= A xnor B
17
Domino CMOS Logic
An Example of Multiple-Output Domino Circuits
C
1
=G
1
+P
1
C
0
C
2
=G
2
+P
2
G
1
+P
2
P
1
C
0
C
3
=G
3
+P
3
G
2
+P
3
P
2
G
1
+P
3
P
2
P
1
C
0
C
4
=G
4
+P
4
G
3
+P
4
P
3
G
2
+P
4
P
3
P
2
G
1
+P
4
P
3
P
2
P
1
C
0

P
1
C
0
P
2
P
3
P
4
G
2
G
3
G
1
G
4
C
4
C
3
C
2
C
1
V
DD
G
i
=A
i
B
i
P
i
=A
i
B
i
Reduce transistor count
18
NORA CMOS Logic (NP-Domino Logic)
Advantages
An Inverter is not required at the output of stages
Allow pipelined system architecture
Disadvantages: Also suffer from charge sharing and
leakage
V
DD
V
DD
V
DD

nMOS
Logic
pMOS
Logic
nMOS
Logic

to nMOS stage to pMOS stage
nMOS stage
precharge
pMOS stage
pre-discharge
all stages
evaluate
nMOS stage
precharge
pMOS stage
pre-discharge
all stages
evaluate

19
NORA CMOS Logic (NP-Domino Logic)
Examples
V
DD
V
DD
V
DD

=L: nMOS precharges to H, and pMOS pre-discharges
to L.
=LH: All cascaded nMOS and pMOS logic stages
evaluate one after the other.