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Finite state machines

Combinational
x
v
1
+
v
0
+
v
0
v
1
w
Huffman Model
clock
Storage
elements
A combinational circuit and storage elements are interconnected to form
a sequencial circuit.
The information stored at any time defines the state of the circuit at
that time.
The next state of the storage elements is a function of the inputs and
the present state.
Synchronous sequential circuit can be defined from the knowledge of its
signals at discrete instants.
Sequential Circuits
Question for You

Logic blocks are classified as:
Combinational and
Sequential
Does sequential logic contain both
combinational logic and memory?
Yes
No

Combinational and Sequential Logic
Combinational logic does not have memory
It generates output solely according to the input and
does not care about history
Often, we need a different reaction on the same input
depending on the current state
E.g.
Current state is 7 and input is 1, the new state and
output are 8
Current state is 15 and input is 1, the new state
and output are
To make the new state depends on the previous
state, we need memory

Sequential Logic and FSM

Computers are made of sequential logic
blocks
Truth tables are used to design combinational
logic, but cant be used to design sequential
logic
Finite state machines (FSM) are used instead
FSM describes a sequential logic block in
terms of:
Set of states,
State transition function (defined on current state
and input), and
Output function (defined on current state and input,
or on current state only)
Why State Machines?
Goal: provide simple abstractions of complex
systems
All computer systems are state machines
registers and memory are state
changes are transitions between states
a program defines the way in which initial states are
transformed into final states
a programming language determines a set of
programs (and hence, a set of machines)
Primary challenge will be to represent these very
complex machines with simpler (more abstract)
machines that we can reason about

State Machines Are Often Used
When it is possible to abstract away irrelevant
details, leaving only a small number of states

When we want to examine every possibility
using exhaustive checking

For communication protocols and complex
distributed algorithms (e.g., cache coherency)

Informally ...
A state machine captures the idea that a system
progresses through a set of states by performing
(or responding to) a set of actions.
Thus there are two key concepts
States
Actions
A state machine definition must say
what the possible states are
what initial states the machine may start in
what the possible actions are
how the state changes when actions occur

A (Very) Simple State Machine
World's simplest (and most boring) state
machine





States: {stop}
Actions: {}
Initial state: {stop}

stop

Another Simple Example
States: {alarm}
Actions: {beep}
Initial state: {alarm}
alarm
beep
Moore vs. Mealy Machines
Definitions
Moore Machine

Outputs are function
solely of the current
state
Outputs change
synchronously with
state changes
Mealy Machine

Outputs depend on
state AND inputs
Input change causes
an immediate
(asynchronous)
output change
State
Register
Clock
State
Feedback
X
Inputs
Z
Outputs
Combinational
Logic for
Next State
(FF Inputs)
Comb.
Logic for
Outputs)
Mealy only; no connection for Moore
Moore

Moore machines are faster
Mealy machines are smaller
Any Moore machine can be turned into a
Mealy machine (and vice versa)


Instead of using algebraic equations for next state
and outputs of sequential network, it is more
convenient and useful to express the information in
tabular form.
Transition Tables :
The Transition Table or State Transition Table or State Table is the
tabular representation of the transition and output equations. This
table consist of Present State, Next State, external inputs and
output variables. If there are n state variables then 2
n
rows are
present in state table.
State machine notations :
Input Variables : External input variables to sequential machine
as inputs.

Output Variables : All variables that exit from the
sequential machine are output variables.
State : State of sequential machine is defined by the content of
memory, when memory is realized by using FFs.
Present State : The status of all state variable i.e. content of FF
for given instant of time t is called as present state.
Next State : The state of memory at t+1 is called as Next state.
State Diagram : State diagram is graphical representation of
state variables represented by circle. The connection between
two states represented by lives with arrows and also indicates
the excitation input and related outputs.

Sequential Circuit Analysis (cont.)
Generate State Diagram
Circles (nodes) represent current or present state values
Lines (arcs) represent how state and output values change
Given the current state and current inputs, the next state
and output values are indicated by the associated arc
State diagram can have different forms depending on the type of
sequential circuit output.
Present
State
Value
Next
State
Value
Inputs/outputs

Output Variables : All variables that exit from the
sequential machine are output variables.
B
1
A
0
Q0
11/10
Q1
x0
11/01
State diagram of J-K FF
0X
Application Table of FF
PS NS FF input
Q Q
+
J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Application Table of FF
PS NS FF i/p
Q Q
+
S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
State diagram of SR FF
0 1
01
00
10
01
00
10

Application Table of FF
PS NS FF i/p
Q Q
+
D i/p
0 0 0
0 1 1
1 0 0
1 1 1
State diagram of D FF
0 1
0
1
0
1

Application Table of FF
State diagram of T FF
0 1
0
1
1
0
PS NS FF i/p
Q Q
+
T i/p
0 0 0
0 1 1
1 0 1
1 1 0



FLIP FLOPS AND THEIR APPLICATIONS


1.





Sequential analysis

x Q Q Q x Z
Q Q Q x D
Q Q Q x D
2 1 1
2 1 1 2
2 1 2 1



1 2 1 1 2
2 1 1
2 1 2 1 2 1
and y x x
and
and
Q y y x K Q Q J
y x Q K y J
Q Q Z Q Q Z




To convert excitation expression into next state
expression, it is necessary to use the characteristic
equations of flip-flops.
Transition Equations :
The characteristic equations of FF depends on types of FF used.
Ex : For D FF Q
+
= D
For JK FF
Q K Q J Q

For T FF
Q
+
= T Q
By substituting the excitation expressions for a FF into
characteristic equation, an algebraic description of next state of
FF is obtained.

The expression for next state in terms of FF inputs
are referred as transition equations.
Q
1
+
= D
1
and Q
2
+
= D
2

For Moore network
2 1 1 2
2 1 2 1
Q Q Q x Q
Q Q Q x Q

1 2 2 2 2
1 1 1 1 1
Q K Q J Q
Q K Q J Q

By substituting the values of J & K inputs we get next state in


terms of FF present state and external input.

Analysis of Sequential Circuits
Example 2
FF input Equations:

DA=AX+BX
DB=AX
A+=DA
B+=DB

Output:
Y=X(A+B)


Analysis of Sequential Circuits
State Table:

Basic Design Approach
Sequential Circuit design: Reverse of analysis
State diagram State table next s.e.
FF input eq. Circuit Diagram

Six Step Process

1. Understand the statement of the Specification
2. Obtain an abstract specification of the SSC
3. Generate State Table
4. Perform state assignment
5. Choose FF types to implement SSC state register
6. Implement the SSC


Sequential Circuit Design
1- Obtain either the state diagram or state table from the
problem specs.
2- If we dont have one already, obtain the state table
from the state diagram.
3- Assign binary codes to the states.
4- Derive the FF input equations from the next state
entries of the state table.
5- Derive the output equations from the output entries of
the state table.


Sequential Circuit Design
Design a sequence detector for the string 1101. The
output must be 1 when the input matches this string
x
w
clock
Sequence
detector

Sequential Circuit Design
Mealy state machine (remember that in this state machine
the output is dependent on input changes and states)
A B C D
0/0
1/0
1/0
1/0
0/0
0/0
1/1
0/0
Assign binary values to each state. Example:
A = 00, B = 01, C = 11, D = 10

Sequential Circuit Design
J K Q(t+1) Operation
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q(t) Complement
Make Table FROM present state & input TO next state &
output, and FF inputs.
A
B
C
D

Sequential Circuit Design
K-maps of the states & the outputs
I
Q1 Q0
J1
0 0 0 1 1 1 1 0
0 0 0 X X
1 0 1 X X
0 0 0 1 1 1 1 0
0 X X 0 1
1 X X 0 1
I
Q1 Q0
K1
0 0 0 1 1 1 1 0
0 0 X X 0
1 1 X X 1
I
Q1 Q0
J0 = I
0 0 0 1 1 1 1 0
0 X 1 1 X
1 X 0 0 X
I
Q1 Q0
K0 = I
= IQ0 = Q0
0 0 0 1 1 1 1 0
0 0 0 0 0
1 0 0 0 1
I
Q1 Q0
Output = IQ1Q0

Sequential Circuit Design
Layout Diagram

J1 = IQ0
K1 = Q0
J0 = I
K0 = I
Output = IQ1Q0

Moore State Machine for the sequence detector 110
Sequential Circuit Design
clock
x
w
A B C D state A
A/0 B/0 C/0 D/1
0
1
1
1 0
0
1
0

Basic Design Approach

Example 1:Sequence Recognizer
Single input X, Single output Z
Reset input
Recognize the sequence 1101
Whenever there is the previous sequence 110at the
input and present input is 1, output should be1.
Example sequences
X: 001100110111101100110111
Y: 000000000100001000000100
Mealy machine: Output depends of present input and
past states

Basic Design Approach
Construct the State Diagram
Machine should remember that the previous values
were 110
Start with an arbitrary state A (start state)with no inputs
yet
Go to a new state B if the input is 1(first 1state)
Go to new state C if the input is 1 again(second 1
state)
Go to a new state D if the input is 0 (110 remembering
state)
With a new 1, go to A and make output 1.

Designing Finite State Machines
Specify the problem with words
(e.g. Design a circuit that detects three consecutive 1
inputs)
Assign binary values to states
Develop a state table
Use K-maps to simplify expressions
Flip flop input equations and output equations
Create appropriate logic diagram
Should include combinational logic and flip flops

Example: Detect 3
Consecutive 1 inputs
State S
0
: zero 1s detected
State S
1
: one 1 detected
State S
2
: two 1s detected
State S
3
: three 1s detected

0
Note that each state has 2 output arrows
Two bits needed to encode state

State Table for Sequence Detector
Sequence of outputs, inputs, and flip flop
states enumerated in state table
Present state indicates current value of
flip flops
Next state indicates state after next rising
clock edge
Output is output value on current clock
edge

Present
State
Next
State
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1
Output
Input
S
0
= 00
S
1
= 01
S
2
= 10
S
3
= 11

Finding Expressions for Next State and Output Value
Create K-map directly from state table (3 columns = 3 K-
maps)
Minimize K-maps to find SOP representations
Separate circuit for each next state and output value


Circuit for Consecutive 1s Detector
Note location of state flip
flops
Output value (y) is
function of state
This is a Moore machine.


Concept of the State Machine
Example: Odd Parity Checker
Even
[0]
Odd
[1]
Reset
0
0
1
1
Assert output whenever input bit stream has odd # of 1's
State
Diagram
Present State
Even
Even
Odd
Odd
Input
0
1
0
1
Next State
Even
Odd
Odd
Even
Output
0
0
1
1
Symbolic State Transition Table
Output
0
0
1
1
Next State
0
1
1
0
Input
0
1
0
1
Present State
0
0
1
1
Encoded State Transition Table
Note: Present state and output are the same value
Moore machine
Concept of the State Machine

Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
D
R
Q
Q
Input
CLK
PS/Output
\Reset
NS

Vending Machine FSM
Step 1. Specify the problem
Vending
Machine
FSM
N
D
Reset
Clk
Open
Coin
Sensor
Gum
Release
Mechanism
Deliver package of gum after 15 cents deposited

Single coin slot for dimes, nickels

No change

Design the FSM using combinational logic and flip flops

Vending Machine FSM
State Diagram
Reset
N
N
N, D
[ open]
15
0
5
10
D
D
Reuse states
whenever possible
Symbolic State Table
Present
St at e
0



5



10



15
D
0
0
1
1
0
0
1
1
0
0
1
1
X
N
0
1
0
1
0
1
0
1
0
1
0
1
X
I nput s Next
St at e
0
5
10
X
5
10
15
X
10
15
15
X
15
Output
Open
0
0
0
X
0
0
0
X
0
0
0
X
1

Vending Machine
FSM
State Encoding
Next State
D
1
D
0
0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X
Present St at e
Q
1
Q
0
0 0



0 1



1 0



1 1
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
N
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
I nput s Output
Open
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
How many flip-flops are needed?

Vending Machine FSM
Determine F/F implementation
K-map for Open
K-map for D0 K-map for D1
Q1 Q0
D N
Q1
Q0
D
N
Q1 Q0
D N
Q1
Q0
D
N
Q1 Q0
D N
Q1
Q0
D
N

D Q
Q R
D Q
Q R
Q
0

N
N
Q
0

Q
1

N
Q
1

D
D
0

D
1
Q
1

OPEN
D
0
Q
N
CLK
CLK
Vending machine FSM implementation based on D flip-flops(Moore).
0
Q
1
Q
Q
1

Q
0

Reset
Reset
Minimized Implementation

Summary
Finite state machines form the basis of many digital
systems
Designs often start from clear specifications
Develop state diagram and state table
Optimize using combinational design techniques
Mealy or Moore implementations possible
Can model approach using HDL.