N.

Senthil Kumar,
M. Saravanan &
S. Jeevananthan

MEMORY AND I/O INTERFACING
Oxford University Press 2013





Physical Memory
Organization in 8086
Since 8086 has 20 address lines, it can access 1 Mbyte
(=220 byte) of memory and memory address in one
Mbyte memory ranges from 00000H to FFFFFH.
The memory is constructed using RAM and ROM
/EPROM chips. The 1 Mbyte memory in 8086 is
physically organized as an odd bank and an even bank,
each of 512 Kbytes, addressed in parallel by the 8086.
Each memory location stores one byte of data.

Oxford University Press 2013





Physical Memory
Organization in 8086
Byte data at an even memory address is transferred
through the 8 bit data bus (D7-D0) while the byte data
at an odd memory address is transferred through the 8
bit data bus (D15-D8).
8086 provides two enable signals and A0 for the
selection of either even or odd or both the banks.
8086 is a 16-bit processor and hence it can transfer
two bytes of data in one memory read or write cycle
(or I/O read or write cycle).
Oxford University Press 2013
Physical Memory
Organization in 8086
Two memory locations are needed to store a word in
memory. While referring word data (16 bits), the bus
interface unit of 8086 requires one or two memory
cycles, depending upon whether the lower byte of the
word is located at an even or odd memory address
respectively.
It is better to store the word type data in memory such
that its lower byte is stored at an even memory
address since only one read cycle is required to read
the data through the 16- bit data bus (D15-D0) of 8086.


Oxford University Press 2013
Physical Memory
Organization in 8086


If the lower byte of the word is located at an odd
memory address, the first read cycle is required for
accessing the lower byte of the word through the higher
data bus (D15-D8) and the second one is required for
accessing the upper byte of the word through the lower
data bus (D7-D0).


Oxford University Press 2013
Oxford University Press 2013
Physical Memory
Organization in 8086
Thus two bus cycles are required to access a word
whose lower byte is stored in an odd memory address
in memory. While initializing the data structures such
as array of word type data and stack, they should be
initialized at an even address for efficient operation.
The above discussion is also applicable to memory
write operation.
Oxford University Press 2013
Function of
BHE and AO Signals
Oxford University Press 2013
Formation of System Bus
The 8086 has a multiplexed 16 bit address/data bus
(AD15-AD0) and a multiplexed four bit address /status
bus A16/S3 A19/S6.
The multiplexed address bus can be split into
separate address bus and data bus /status bus using
ALE (Address latch enable) signal of 8086 and three
external octal latches (IC 74373
The 8086 has multiplexed 16 bit data bus in the form
of AD15-AD0. The data can be separated from the
address and buffered using two bidirectional buffers
74245.
Oxford University Press 2013
Formation of System Bus
Since data can flow in either direction from or into
microprocessor while accessing memory or I/O
devices, bidirectional buffers are used for deriving the
data bus.
The signals and DT/ indicate the presence of data on
the bus and the direction of the data that is from/to
the microprocessor respectively and they are
connected to the chip enable and direction pins of the
buffers.
Oxford University Press 2013
Formation of System Bus
Certain locations in memory are reserved for specific
CPU operations. After reset of 8086, CS and IP are
initialized to FFFFH and 0000H respectively and the
first instruction for execution will be taken from the
address FFFF0H in memory.
Hence the locations from FFFF0H to FFFFFH in
memory are reserved for storing instructions,
execution of which causes the 8086 to jump to the
initialization program of the system. The memory
locations 00000H to 003FFH are reserved for interrupt
vector table.
Oxford University Press 2013
Formation of System Bus
These memory locations are assigned to ROM/EPROM
chips in an 8086 based system so that the programs
stored in them are permanent. The interrupt vector
table may be located in RAM chips in some systems.
The memory chips can be interfaced with 8086 using
only logic gates or using both logic gates and decoder
IC (74138).
Oxford University Press 2013
Interfacing RAM and
EPROM Chips Using Only
Logic Gates
Interface two 8KX8 EPROMS (2764) and two 8KX8 RAM
chips (6264) with 8086 such that the memory
addresses range assigned to EPROM and RAM chips are
from FC000H to FFFFFH and from 00000h to 03FFFH
respectively using logic gates.
Oxford University Press 2013
Interfacing RAM and
EPROM Chips Using Only
Logic Gates
Solution:
First let us see the interfacing of the two 8KX8 EPROM
chips with 8086 to have the address from FC000H to
FFFFFH.
Oxford University Press 2013
Interfacing RAM and
EPROM Chips Using Only
Logic Gates
Oxford University Press 2013
Interfacing RAM and
EPROM Chips Using Only
Logic Gates
The even addresses such as FC000H, FC002H, FC004H,
etc. are assigned to one 8K X 8 EPROM chip (say 2764-
A) which acts as even memory bank and odd addresses
such as FC001H, FC003H, FC005, etc. are assigned to
another 8K X 8 EPROM chip (say 2764-B) which acts as
odd memory bank.
Oxford University Press 2013
Interfacing RAM and
EPROM Chips Using Only
Logic Gates
Since A0 is 0 for all even addresses, it is used to
generate the chip select or chip enable signal for 2764-
A along with some of the higher order address lines of
8086.
Similarly is used along with some of the higher order
address lines of 8086 to select the odd memory bank
formed by 2764-B.
Oxford University Press 2013
Interfacing RAM and EPROM
Chips Using Only Logic Gates
First the number of address lines in the 8KX8 EPROM
chip is noted which is 13 (A12-A0) since 213=8k.
The address lines A1 to A13 of 8086 are connected to
the address lines A0 to A12 of 2764-A and 2764-B,
since address line A0 of 8086 is used for selecting the
even memory bank.
The remaining address lines A19 to A14 of 8086 are
used for address decoding.
Oxford University Press 2013
Memory Addresses
Assigned To RAM Chips
Oxford University Press 2013
Interfacing RAM/EPROM
Chips Using Decoder IC and
Logic gates
Interface two 8KX8 EPROM chips with 8086 such that the
memory addresses range assigned to EPROM chips are
from FC000H to FFFFFH using address decoder made up of
74138 IC and logic gates.
The thirteen address lines (A0 to A12) in 2764 are
connected to the address lines (A1 to A13) in 8086
respectively. For the entire address range FC000H to
FFFFFH, the value in the address lines A19 to A14 are equal
to 1.
Oxford University Press 2013
Interfacing RAM/EPROM
Chips Using Decoder IC and
Logic gates
The address lines A19 to A15 are used to enable the
74138 decoder IC and the address line A14, A0 and
are connected to the selection lines of 74138 IC.
Figure 16.10 shows the interfacing of the EPROM chips
with 8086 chips using 74138 decoder. For
simplification, only the decoder and EPROM chips are
shown.
Oxford University Press 2013
Selection of EPROM Chips
Oxford University Press 2013
I/O Interfacing
The operation of I/O instructions (IN and OUT), the
concept of I/O mapped I/O and memory mapped I/O
and the interfacing of simple I/O devices such as DIP
switch and LEDs with 8086 are discussed.
The IN instruction is used to read data from input
device to AL or AX in 8086. The OUT instruction is used
to send data in AL or AX to an output device. The I/O
devices address is either stored in register DX as a 16-
bit I/O address or in the byte immediately following
the opcode of IN/Out instruction as an 8-bit I/O
address.
Oxford University Press 2013
I/O Interfacing
Whenever data are transferred using the IN or OUT
instruction, the I/O devices address often called a port
number appears on the address bus. The external I/O
interface decodes the address in the same manner as
decoding a memory address to select a particular I/O
device. The 8-bit fixed port number appears on address
lines A7-A0 with address lines A15-A8 as 00H. The
address lines A15-A19 are undefined for an I/O
instruction. The 16-bit port number in DX appears on
address lines A15-A0.
Oxford University Press 2013
I/O Instructions in 8086
Oxford University Press 2013
I/O mapped I/O and
Memory mapped I/O
There are two different methods of interfacing I/O
devices to the 8086 same as that of interfacing 8085
with I/O devices.
They are I/O mapped I/O and Memory mapped I/O
schemes. In I/O mapped I/O scheme, IN and OUT
instructions are used to transfer data between
microprocessor and I/O devices.
In memory mapped I/O, any instruction that references
memory can be used to do the same data transfer.

Oxford University Press 2013
I/O Mapped I/O
The most common I/O data transfer technique used in
Intel microprocessor based system is I/O mapped I/O
and it is also known as isolated I/O scheme.
The term isolated represents that the I/O locations
are isolated from the memory system in a separate I/O
address space The address for isolated I/O devices,
called ports, is separate from the memory in isolated
I/O scheme. As a result, the user can expand the
memory to its full size (i.e 1 MB) without using any of
this space (00000H to FFFFFH) for I/O devices.
Oxford University Press 2013
I/O Mapped I/O
A disadvantage of I/O mapped I/O is that data
transferred between 8086 and I/O devices must be
accessed only by the IN and OUT instructions. Separate
control signals for the I/O devices are generated that
indicate an I/O read (IOR) or an I/O write (IOW)
operation.
In maximum mode operation of 8086, the IOWC and
IORC signal generated by 8288 bus controller is used to
interface I/O devices with 8086.
Oxford University Press 2013
Memory Mapped I/O
The memory mapped I/O scheme does not use the IN
and OUT instructions. Instead any instruction that
transfers data between the microprocessor and
memory can be used for transferring data between
8086 and I/O devices.
The main advantage of this scheme is that there are
memory transfer instructions in 8086 and all of them
can be used to access the I/O device.
Oxford University Press 2013
Memory Mapped I/O
The same control signals used for accessing memory (MEMR
and MEMW in minimum mode and MRDC and MWTC from
8288 in maximum mode) are used for accessing I/O devices
which reduces additional circuitry needed to generate the
control signals.
The main disadvantage of memory-mapped I/O scheme is that
a portion of the memory system is used as the I/O map.
This reduces the amount of memory available to the
applications. Since I/O mapped I/O scheme is commonly used
in 8086 based system, it is discussed in detail in the following
sections.
Oxford University Press 2013. All rights reserved.

Oxford University Press 2013
Interfacing 8-bit input device
with 8086
To interface an input device with 8086, three-state
buffers are used. Typical example for three-state buffer
IC is 74LS244.
Depending upon whether 8-bit or 16-bit address is to
be assigned to the DIP switch, the construction of
address decoder differs.
The address decoder can be constructed only using
logic gates or combination of logic gates and decoder IC
such as 74LS138.
Oxford University Press 2013
Assigning 8-bit address to an 8-bit input
device using address decoder having only
logic gates
Let us interface an 8-bit DIP switch with 8086
operating in minimum mode such that the address
assigned to it is 8FH using address decoder having
only logic gates.
When the 8086 has to read the data from the 8-bit
DIP switch the instruction IN AL, 8FH (or) IN AL, DX
with DX already loaded with the value 008FH has to
be executed by it.
Oxford University Press 2013
Assigning 8-bit address to an 8-bit input
device using address decoder having
only logic gates
During the execution of any one of the above instructions, the
address lines A7-A0 will contain 8FH and the IOR signal is made
low for some duration (few s) by 8086, due to which the
enable inputs (`1G and 2G) of the 74LS244 are activated (i.e.
made low) and the data from the DIP switch is placed on the
data bus (D15-D8) and the 8086 reads that data and places it in
AL register.
The data bus D7-D0 is used if the I/O device address is an even
number.
Oxford University Press 2013
Assigning 8-bit address to an 8-bit
input device using
address decoder IC (74LS138)
When the 8086 places the address 8FH (10001111 in
binary) in the address lines A7-A0, the inputs C=B=A=1,
G1=1 and G2A=G2B=0 in the 74LS138 IC, due to which
the decoder IC is enabled and its Y7 output goes low
and other outputs remain high.
Oxford University Press 2013
Assigning 8-bit address to an 8-bit input
device using
address decoder IC (74LS138)
This Y7 output of decoder IC along with the IOR signal
of 8086 is used to enable the 74LS244 IC thereby
transferring data from the DIP switch to AL register of
8086 as explained in the previous section.
The same decoder ICs other outputs (i.e Y0 to Y6) can
be used to assign the addresses (88H to 8EH
respectively) to other I/O devices.
Assigning 16-bit address to an 8-bit DIP
switch using address decoder having
only logic gates
Oxford University Press 2013
When the 8086 executes the instruction IN AL,DX
with DX already loaded with the value FFF0H (This is
done using MOV DX, FFF0H instruction), it places the
address FFF0H in the address lines A15-A0 and
activates the IOR signal for some duration (few s).
This makes 1G and 2G of the 74LS244 to go to low
state thereby enabling the 74LS244 and data from the
DIP switch is placed in the data bus (D7-D0) of 8086.

Assigning 16-bit address to an 8-bit DIP
switch using address decoder having
only logic gates
Oxford University Press 2013
The 8086 reads that data and places it in AL register.
Similarly the 16-bit address decoder can be designed
using combination of logic gates and decoder IC
(74LS138) as explained in 8-bit address decoder
construction using combination of logic gates and
74LS138.
Interfacing 8-bit output device
with 8086
Oxford University Press 2013
To interface an output device with 8086, latches are
used. Typical example for octal latches IC is 74LS373.
Either an 8-bit or 16-bit address can be assigned to
the set of LEDs as explained in the interfacing of input
devices with 8086 and here also the address decoder
can be constructed either using only logic gates or the
combination of logic gates and decoder IC such as
74LS138.

Interfacing 8-bit output device with
8086
Oxford University Press 2013
Let us see the interfacing of an 8-bit output device
having 8-bit address. When the 8086 has to send the
data in AL register to the LEDs, either the instruction
OUT F0H, AL (or) OUT DX, AL with DX already loaded
with the value 00F0H has to be executed by it.
During the execution of any one of the above
instructions, the address lines A7-A0 will contain F0H
and the data lines D7-D0 will contain the data in AL
register and IOW signal (Let us assume that the 8086 is
operating in minimum mode) is made low for same
duration (few s) by 8086.
Interfacing 8-bit output device with
8086
Oxford University Press 2013
This activates (i.e. makes high) the clock (CLK) signal
of 74LS373 IC and the data in the data bus D7-D0
which is the content of AL register is latched in the
74LS373 IC and it is hold there until OUT instruction
with the same address is again executed by 8086. The
OC pin in the 74LS373 IC is made low to enable the
tri-state inverter connected to each output pin.
Interfacing 8-bit or 16-bit I/O devices or
ports with 8086
Oxford University Press 2013
Let us see how data are transferred between 8086 and
8 or 16-bit I/O devices. Data transferred to an 8-bit I/O
device or I/O port exists in one of the I/O banks of the
8086.
The I/O system contains two 8-bit I/O banks just as the
memory system of 8086. This is shown in fig. 16.22
which indicates the separate I/O banks for a 16-bit
system. When 8-bit address is used for I/O devices, the
even bank contains even addresses such as 00H, 02H,
04H, etc and odd bank contains odd addresses such as
01H, 03H, 05H, etc
Interfacing 8-bit or 16-bit I/O devices
or ports with 8086
Oxford University Press 2013
When 16-bit address is used for I/O devices, the even
bank contains even addresses such as 0000H, 0002H,
0004H, etc and odd bank contains odd addresses such
as 0001H, 0003H, 0005H, etc.
Because two I/O banks exist, any 8-bit I/O write
requires separate write strobes to function correctly
which are generated. I/O reads do not require
separate read strobes because, as with memory, the
8086 only reads the byte it expects and ignores the
other byte.
Summary
Oxford University Press 2013
The maximum memory that can be connected with
8086 is 1Mbytes which is organized as two separate
banks namely even or low memory bank and odd or
high memory bank.
The signal is used to enable the odd memory bank
and the data lines of the odd memory bank are
connected with the data lines D15-D8 of 8086.
The address line A0 is used to enable the even
memory bank and the data lines of even memory
bank are connected to the data lines D7-D0 of 8086.
Summary
Oxford University Press 2013
When the lower byte of a word is stored in even
memory bank, 8086 can access both bytes of that
word in a single memory read cycle otherwise it takes
two memory read cycles to read the same word. Due
to this reason, while storing an array of word type
data in memory or while initializing the stack, the
lower byte of words are stored in even addresses.
There are two methods that can be used to interface
I/O devices with 8086 namely memory mapped I/O
and I/O mapped I/O.
Summary
Oxford University Press 2013
In the memory mapped I/O method, the I/O device is
treated as if a memory location and the instructions
used for transferring data between memory and 8086
can be used for data transfer between 8086 and I/O
devices. The and signals are used to activate input
and output device respectively. The I/O device will
have 16-bit address in memory mapped I/O and
design of address decoder is same as that of memory
address decoder.
Summary
Oxford University Press 2013
The I/O mapped I/O scheme is commonly used to
interface I/O device with 8086. Here there are two
methods of addressing I/O devices namely fixed port
addressing, in which the 8-bit address of an I/O device
is specified in the IN or OUT instruction directly and
variable port addressing, in which the 16-bit address of
an I/O device is specified in the IN or OUT instruction
implicitly through DX register. In I/O mapped I/O, only
IN and OUT instruction are used to communicate with
I/O devices and the advantage of this method is that
the user can fully utilize the 1Mbyte memory space
which is not possible in memory mapped I/O.

Summary
Oxford University Press 2013
8086 can be interfaced to either 8-bit or 16-bit port. The
I/O space in 8086 is also organized as two separate I/O
banks namely odd and even I/O bank, same as memory
organization in 8086. The odd I/O bank contains odd I/O
addresses and the data lines of odd I/O bank are
connected to D15-D8 lines of 8086. The even I/O bank
contains even I/O addresses and the data lines of even
I/O bank are connected to D7-D0 lines of 8086. The
signal is used to enable the odd I/O bank and A0 is used
to enable the even I/O bank same as enabling memory in
8086. The and signals are used to activate the input and
output devices respectively in I/O mapped I/O scheme.
Key Terms
Oxford University Press 2013
Even or Low memory bank Memory chip/chips that
contain even memory addresses and its data lines are
connected to D7-D0 lines of 8086.
Odd or High memory bank Memory chip/chips that
contain odd memory addresses and its data lines are
connected to D15-D8 lines of 8086.
MEMR Memory read control signal which is activated
during memory read operation.
MEMW Memory write control signal which is
activated during memory write operation.
- Bus High Enable signal used to enable the upper bank of
memory in 8086.
Key Terms
Oxford University Press 2013
Physical memory address Memory address in the
physical memory such as RAM or EPROM chip.
Memory address space or Memory Map The possible
memory addresses that can be generated by 8086 which
is 00000H to FFFFFH.
Memory mapped I/O A method of interfacing I/O
device with 8086 in which an I/O device is treated as if a
memory location.
I/O mapped I/O A method of interfacing I/O device
with 8086 in which an I/O device is treated separately
from memory.
Key Terms
Oxford University Press 2013
IOR I/O read control signal which is activated during
I/O read operation.
IOW I/O write control signal which is activated during
I/O write operation.
Tri-state buffer Used for interfacing input device with
microprocessor.
IN & OUT instruction Used for transfer data between
accumulator and I/O devices in I/O mapped I/O.
8-bit Input device Input device which sends 8-bit data
to 8086.
16-bit Input device Input device which sends 16-bit data
to 8086.

Key Terms
Oxford University Press 2013
8-bit Output device Output device which receives 8-bit
data from 8086.
16-bit Output device Output device which receives 16-
bit data from 8086.
Low or even I/O bank- I/O bank which contain even
addresses and is connected to the data lines D7-D0 of
8086.
High or odd I/O bank- I/O bank which contain odd
addresses and is connected to the data lines D15-D8 of
8086.