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CISC (Complex Instruction Set Computer) is a microprocessor architecture that utilizes a large set of instructions that are easy to program and make efficient use of memory. Common CISC designs like Intel 80x86 and Motorola 68K use complex instructions that may take multiple clock cycles to execute. In contrast, RISC (Reduced Instruction Set Computer) utilizes a small, highly optimized set of single-cycle instructions and emphasizes register use and efficient instruction pipelining over complex instructions.
CISC (Complex Instruction Set Computer) is a microprocessor architecture that utilizes a large set of instructions that are easy to program and make efficient use of memory. Common CISC designs like Intel 80x86 and Motorola 68K use complex instructions that may take multiple clock cycles to execute. In contrast, RISC (Reduced Instruction Set Computer) utilizes a small, highly optimized set of single-cycle instructions and emphasizes register use and efficient instruction pipelining over complex instructions.
CISC (Complex Instruction Set Computer) is a microprocessor architecture that utilizes a large set of instructions that are easy to program and make efficient use of memory. Common CISC designs like Intel 80x86 and Motorola 68K use complex instructions that may take multiple clock cycles to execute. In contrast, RISC (Reduced Instruction Set Computer) utilizes a small, highly optimized set of single-cycle instructions and emphasizes register use and efficient instruction pipelining over complex instructions.
Computer & are chips consists of large no of instruction set that are easy to program and make efficient use of memory. Most common microprocessor designs such as the Intel 80x86 and Motorola 68K series followed the CISC philosophy. CISC was developed to make compiler development simpler.(Adding instruction which facilitate to translate high-level language into machine language)
5/22/2014 1 Characteristics of CISC Simplify compilation & improves overall performance. (uses complex instruction to implement the statements directly ). Variable length insruction format ,hence require complex decoding circuits. Instructions which require multiple clock cycles to execute. A small number of general purpose registers.
5/22/2014 2 Several special purpose registers such as SP,interrupt which can simplify the hardware design somewhat, at the expense of making the instruction set more complex. Large variety of addressing modes- 5 to 20. Operands during manipulation for an instruction is memory. Microprogramniing is as easy as assembly language to implement, and much less expensive than hardwiring a control unit. 5/22/2014 3 Disadvantages Earlier generations of a processor family generally were contained as a subset in every new version - so instruction set & chip hardware become more complex with each generation of computers. So that as many instructions as possible could be stored in memory with the least possible wasted space, individual instructions could be of almost any length - this means that different instructions will take different amounts of clock time to execute, slowing down the overall performance of the machine.
5/22/2014 4 What is RISC? RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions . History The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC.
5/22/2014 5 Characteristics of RISC Reduced instruction set. Less complex, simple instructions. Hardwired control unit and machine instructions. Few addressing schemes Memory access for operands with only two basic instructions, LOAD and STORE Many symmetric registers which are organised into a register file. Fixed length ,easily decoded instruction format
5/22/2014 6 Single cycle instruction execution. Use of large no registers makes the processor faster than memory access. Efficient instruction pipeline. Compiler support for efficient translation of high level language programs into machine language programs 5/22/2014 7 CISC
RISC
Emphasis on hardware
Emphasis on software
Includes multi-clock complex instructions
Single-clock, reduced instruction only
Memory-to-memory: "LOAD" and "STORE" incorporated in instructions
Register to register: "LOAD" and "STORE" are independent instructions