DESIGN AND PERFORMANCE ANALYSIS OF LOW

POWER DIGITAL CIRCUITS USING GDI

SUBMITTED BY:
POOJA VERMA
ROLL NO -1270679
M.TECH- VLSI DESIGN
CHANDIGARH GROUP OF COLLEGES,LANDRAN
PUNJAB TECHNICAL UNIVERSITY
Outline
PREVIOUS WORK

Role of VLSI In digital
circuits
Gaps in present Study
Objectives
Methodology
Review paper
PROGRESSIVE WORK

Design and analyses of
logic gates using MGDI
Average power comparison
of gates
RADIX 4 multiplier using
MGDI
Booth multiplication
Design of multiplier
Full adder schematic




INTRODUCTION
The main idea of this thesis work is design and analyses of low power digital
circuits .Different design techniques such as CMOS, PTL ,TG and gate
diffusion input (GDI) can be used to design digital circuits.

The most efficient technique among all these techniques is GDI technique

Logic gates have been designed using modified GDI technique on TANNER
and simulations have been performed.

RADIX 4 BOOTH multiplier is going to be implemented using modified GDI


Design of logic gates
AND GATE SCHEMATIC

Operation of and gate
For A=0 and B=0: pMOS in Linear: Vin Vtp < Vout < V
nMOS in Cut-off: Vin< Vtn
For A=1 and B=0: pMOS in Cut-off: Vin > VDD + Vtp
nMOS in Linear: 0 < Vout < Vin Vtn
For A=0 and B=1: pMOS in Linear: Vin Vtp < Vout < VDD
nMOS in Cut-off: Vin< Vtn
For A=1 and B=1: pMOS in linear: Vin Vtp < Vout < VDD
nMOS in linear: 0 < Vout < Vin - Vtn
TRANSIENT ANALYSES OF AND GATE

OR GATE SCHEMATIC
TRANSIENT ANALYSES OF OR GATE
NAND GATE SCHEMATIC TRANSIENT ANALYSES OF NAND GATE
NOR GATE SCHEMATIC TRANSIENT ANALYSES OF NOR GATE
XOR GATE SCHEMATIC TRANSIENT ANALYSES OF XOR GATE
Average power comparison of
MGDI gates
BASIC GATES Average power using 250
nm technology
Average power using
180nm technology
AND GATE .986W .00733W
OR GATE 1.20W .0031W
NAND GATE .540W .00235W
NOR GATE .654W .00976W
XOR GATE 1.23W .00438W
RADIX 4 BOOTH MULTIPLIER
USING MGDI
Multiplier is one of the mostly used building blocks in the digital devices. The high
performance DSP systems depend on hardware multiplication to achieve high data
throughput.
Generic multiplier block diagram
Booth multiplication
Booth multiplication is a technique that allows faster multiplication by grouping
the multiplier bits. The grouping of multiplier bits and Radix-4 Booth encoding
reduce the total partial products into half of it.










Dot diagram for 16* 16 bit multiplication











MULTIPLIER DESIGN
Basically Multiplier design consist of three operational steps:

1. BOOTH ENCODER- encode the multiplier bit Y using Booth encoded
algorithm and a partial product is produced from the multiplicand X and
the encoded multiplier Y.

2. PARTIAL PRODUCT GENERATOR- the partial product compression is
used to add all partial products and then reduce them into the form of sum
and carry.

3. ADDER- the final addition using CSA adder or RCA adder in which final
multiplication result is generated by adding sum and the carry .
Full adder schematic
8-T MGDI FULL ADDER SCHEMATIC