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Instruction Data
lw $2, 200($0) 8 ns fetch
Reg ALU
access
Reg
Instruction
lw $3, 300($0) 8 ns fetch
...
8 ns
Program
execution 2 4 6 8 10 12 14
Time
order
(in instructions)
Instruction Data
lw $1, 100($0) Reg ALU Reg
fetch access
Instruction Data
lw $2, 200($0) 2 ns Reg ALU Reg
fetch access
Instruction Data
lw $3, 300($0) 2 ns Reg ALU Reg
fetch access
2 ns 2 ns 2 ns 2 ns 2 ns
3
1998 Morgan Kaufmann Publishers
Pipelining
• We’ll talk about modern processors and what really makes it hard:
– exception handling
– trying to improve performance with out-of-order execution, etc.
4
1998 Morgan Kaufmann Publishers
Basic Idea
IF: Instruction fetch ID: Instruction decode/ EX: Execute/ MEM: Memory access WB: Write back
register file read address calculation
0
M
u
x
1
Add
4 Add Add
result
Shift
left 2
Read
PC Address register 1 Read
data 1
Read
register 2 Zero
Instruction Registers Read ALU ALU
Write 0 Read
data 2 result Address 1
register M data
Instruction M
u Data
memory Write x u
memory x
data 1
0
Write
data
16 32
Sign
extend
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1998 Morgan Kaufmann Publishers
Pipelined Datapath
0
M
u
x
1
Add
Add
4 Add result
Shift
left 2
Read
Instruction
PC Address register 1
Read
data 1
Read
register 2 Zero
Instruction
Registers Read ALU ALU
memory Write 0 Read
data 2 result Address 1
register M data
u M
Data u
Write x memory
data x
1
0
Write
data
16 32
Sign
extend
6
1998 Morgan Kaufmann Publishers
Corrected Datapath
0
M
u
x
1
Add
4 Add Add
result
Shift
left 2
Read
Instruction
7
1998 Morgan Kaufmann Publishers
Graphically Representing Pipelines
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1998 Morgan Kaufmann Publishers
Pipeline Control— These slides depend on this figure and differ from the
text when working with different data path configurations. Most noticeable in
branching.
PCSrc
0
M
u
x
1
Add
Add
4 Add
result
Branch
Shift
RegWrite left 2
Read MemWrite
Instruction
PC Address register 1
Read
data 1
Read ALUSrc
register 2 Zero
Zero MemtoReg
Instruction
Registers Read ALU ALU
memory Write 0 Read
data 2 result Address 1
register M data
u M
Data u
Write x memory
data x
1
0
Write
data
Instruction
[15– 0] 16 32 6
Sign ALU
extend control MemRead
Instruction
[20– 16]
0
M ALUOp
Instruction u
[15– 11] x
1
RegDst
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1998 Morgan Kaufmann Publishers
Pipeline control
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1998 Morgan Kaufmann Publishers
Pipeline Control
WB
Instruction
Control M WB
EX M WB
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1998 Morgan Kaufmann Publishers
Datapath with Control
PCSrc
ID/EX
0
M
u WB
x EX/MEM
1
Control M WB
MEM/WB
EX M WB
IF/ID
Add
Add
4 Add result
RegWrite
Branch
Shift
left 2
MemWrite
ALUSrc
Read
MemtoReg
Instruction
PC Address register 1
Read
data 1
Read
register 2 Zero
Instruction
Registers Read ALU ALU
memory Write 0 Read
data 2 result Address 1
register M data
u Data M
Write x memory u
data x
1
0
Write
data
Instruction 16 32 6
[15– 0] Sign ALU MemRead
extend control
Instruction
[20– 16]
0 ALUOp
M
Instruction u
[15– 11] x
1
RegDst
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1998 Morgan Kaufmann Publishers
Dependencies
Value of CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9
register $2: 10 10 10 10 10/– 20 – 20 – 20 – 20 – 20
Program
execution
order
(in instructions)
sub $2, $1, $3 IM Reg DM Reg
13
1998 Morgan Kaufmann Publishers
Software Solution w/o forwarding
14
1998 Morgan Kaufmann Publishers
Forwarding
Program
execution order
(in instructions)
sub $2, $1, $3 IM Reg DM Reg
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1998 Morgan Kaufmann Publishers
Forwarding
ID/EX
WB
EX/MEM
Control M WB
MEM/WB
IF/ID EX M WB
M
Instruction
u
x
Registers
Instruction Data
PC ALU
memory memory M
u
M x
u
x
IF/ID.RegisterRs Rs
IF/ID.RegisterRt Rt
IF/ID.RegisterRt Rt
M EX/MEM.RegisterRd
IF/ID.RegisterRd Rd u
x
Forwarding MEM/WB.RegisterRd
unit
16
1998 Morgan Kaufmann Publishers
Can't always forward
–
or $8, $2, $6 IM Reg DM Reg
17
1998 Morgan Kaufmann Publishers
Stalling
bubble
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1998 Morgan Kaufmann Publishers
Branch Hazards
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1998 Morgan Kaufmann Publishers
Pipeline Control - These slides depend on this figure and differ from the
text when working with different data path configurations. Most noticeable in
branching.
PCSrc
0
M
u
x
1
Add
Add
4 Add
result
Branch
Shift
RegWrite left 2
Read MemWrite
Instruction
PC Address register 1
Read
data 1
Read ALUSrc
register 2 Zero
Zero MemtoReg
Instruction
Registers Read ALU ALU
memory Write 0 Read
data 2 result Address 1
register M data
u M
Data u
Write x memory
data x
1
0
Write
data
Instruction
[15– 0] 16 32 6
Sign ALU
extend control MemRead
Instruction
[20– 16]
0
M ALUOp
Instruction u
[15– 11] x
1
RegDst
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1998 Morgan Kaufmann Publishers
Flushing Instructions (? details)
IF.Flush
Hazard
detection
unit
M ID/EX
u
x
WB
EX/MEM
M
Control u M WB
x MEM/WB
0
IF/ID EX M WB
4 Shift
left 2
M
u
x
Registers =
Instruction Data
PC ALU
memory memory M
u
M x
u
x
Sign
extend
M
u
x
Forwarding
unit
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1998 Morgan Kaufmann Publishers
Improving Performance
lw $t0, 0($t1)
lw $t2, 4($t1)
sw $t2, 0($t1)
sw $t0, 4($t1)
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1998 Morgan Kaufmann Publishers
Dynamic Scheduling
• This class has given you the background you need to learn more
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1998 Morgan Kaufmann Publishers