STT-RAM Feasibility Study

Amr Amin
UCLA
Jan 2010
Outline
Introduction
Memory Cell
Cell Area Calculation
Write Current Limitations
Reading Techniques and Limitations
Effect of Process Variations and Mismatch
MTJ Feasible Region
Area Minimization
Introduction
The need for a universal memory
Brief history of magnetic device memories
Description of the MTJ device
Literature survey


Summary of the paper flow
STT-RAM Cell
Schematic diagram
Anti-parallelizing / Parallelizing currents
Read disturb problem
Cell layout
Basic cell area vs. access device width
Effective Cell Area
This takes into account the overhead of:
Column MUX
Row decoder
Sense Amp
I/O circuits
Area optimization should also consider:
Optimum memory partitioning
Access transistor vs. column MUX areas
Write Current Limitations
MOS drain current equation and fitting
Maximum allowed R
P
and R
AP
for certain
write current(s)
Column MUX design (justification for using
T-gates instead of P-transistors)
Effect of each of the four MUX devices on
the maximum allowed resistances
NMOS Drain Current
( )
( ) | |
( )
( )
( )
( ) ( )

4
V V
V ;
4
V V
V 1
V V 1
V V
4
L
W
C
4
V V
V 0 ; V V V V
V V 1
L
W
C
I
th GS
DS
th GS
DS
th GS
2
th GS
ox n
th GS
DS
2
DS DS th GS
th GS
ox n
D

>
(

|
|
.
|

\
|
+
+

|
.
|

\
|

s s
+
|
.
|

\
|
=

u
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-200
0
200
400
600
800
1000
1200
1400
1600
Vds (V)
I
d

(

A
)
NMOS Simple Theoritical Model


Vgs=0.8V
Vgs=0.9V
Vgs=1.0V
Vgs=1.1V
Vgs=1.2V
Vgs=1.3V
Vgs=1.4V
Vgs=1.5V
Vgs=1.6V
Vgs=1.7V
Vgs=1.8V
Vgs=1.9V
Vgs=2.0V
PMOS Drain Current
( )
( ) | |
( )
( )
( )
( ) ( )

4
V V
V ;
4
V V
V 1
V V 1
V V
4
L
W
C
4
V V
V 0 ; V V V V
V V 1
L
W
C
I
th GS
DS
th GS
DS
th GS
2
th GS
ox p
th GS
DS
2
DS DS th GS
th GS
ox p
D

>
(

|
|
.
|

\
|
+
+

|
.
|

\
|

s s
+
|
.
|

\
|
=

u
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-100
0
100
200
300
400
500
600
700
Vds (V)
I
d

(

A
)
PMOS Simple Theoritical Model


Vgs=0.8V
Vgs=0.9V
Vgs=1.0V
Vgs=1.1V
Vgs=1.2V
Vgs=1.3V
Vgs=1.4V
Vgs=1.5V
Vgs=1.6V
Vgs=1.7V
Vgs=1.8V
Vgs=1.9V
Vgs=2.0V
Maximum R
AP
V
G
V
G
V
G
V
DD
R
AP
X
I
P
M
N2
M
P1
M
N1
M
P2
M
a
( )
( ) ( )
1
1
1
2
,
0
1
2 2
p
p
n a
n a ox n
Par n
th G n
P n
th G
Par n
n th G
Par
AP,MAX
W
r
W W
W W
L
C
I
V V
I
V V
I
V V
I
V
R
|
|
.
|

\
|
+
|
.
|

\
|
+

q
u
q q
0 500 1000 1500 2000
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
Writing Current (A)
R
A
P
,
M
A
X

(
O
)
Maximum Antiparallel Resistance (R
AP
)


Analytic
Simulation
Maximum R
P
V
G
V
G
V
DD
X
M
N1
M
P2
M
N2
M
P1

V
G
I
AP
M
a
R
P
( ) ( ) ( )
( ) | |
2
,
2
,
2
, ,
1
4 2 2
n
n
n th G n
a
ox n APar
n
APar
n th G
a
ox n
n n
APar
n th G
a
ox n
n n
APar
n th G
P,MAX
W
r
V V
L
W
C I
I
V V
L
W
C
I
V V
L
W
C
I
V V
R +
|
.
|

\
|
+
(

(
(
(
(

|
.
|

\
|

|
.
|

\
|

= u

u q

u q
0 500 1000 1500 2000
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
Writing Current (A)
R
P
,
M
A
X

(
O
)
Maximum Parallel Resistance (R
P
)


Analytic
Simulation
Reading Limitations
Current sensing




Voltage sensing
( )( )
( ) ( )
2
2 1
2
1
2
1
|
|
.
|

\
|
+
|
|
.
|

\
|
+ + +
|
|
.
|

\
|
=
+ +

= A
P
on
P
on
P
R
on P on AP
P AP
R R
R
r
R
r
T T
T
R
V
r R r R
R R
V I
( )
T R I
R R I V
P R
P AP R R
2
1
2
1
=
= A
Constant Read Signal Contours
Current Sensing
P
R
R
on
R
R
P on
R
R
on
R
R
AP
R
V
I
r
V
I
R r
V
I
r
V
I
R
A

|
|
.
|

\
| A
+ +
A
=
2 2 1
2 1 2
2
Voltage Sensing
P
R
R
AP
R
I
V
R +
A
= 2
0 500 1000 1500 2000
0
200
400
600
800
1000
1200
1400
1600
1800
2000
R
P
(O)
R
A
P

(
O
)
Contours of Constant Read Current Signal


AI
R
= 0 A
AI
R
= 20 A
AI
R
= 40 A
AI
R
= 60 A
AI
R
= 80 A
AI
R
= 100 A
AI
R
= 120 A
0 500 1000 1500 2000
0
200
400
600
800
1000
1200
1400
1600
1800
2000
R
P
(O)
R
A
P

(
O
)
Contours of Constant Read Voltage Signal


AV
R
= 0 mV
AV
R
= 20 mV
AV
R
= 40 mV
AV
R
= 60 mV
AV
R
= 80 mV
AV
R
= 100 mV
AV
R
= 120 mV
Process Variations
MOS variations:
Min K and max VT
Reduce the maximum allowed R
P
and R
AP
Mismatch:
Degrades sensitivity of the SA
Higher nominal read margin is required
MTJ variations:
MgO thickness and area variations
Distort the nominal feasible region of the MTJ
Process Variations
( )
nom MgO RA nom
t t K RA RA + =
0 500 1000 1500 2000
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
Writing Current (A)
R
P
,
M
A
X

(
O
)
Maximum Parallel Resistance (R
P
)


Nominal
/w 25%-K and 100mV-VT
/w 0.5A
o
MgO Variation
Nominal: Sim
0 500 1000 1500 2000
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
Writing Current (A)
R
A
P
,
M
A
X

(
O
)
Maximum Antiparallel Resistance (R
AP
)


Nominal
/w 25%-K and 100mV-VT
/w 0.5A
o
MgO Variation
Nominal: Sim
( )
nom MgO TMR nom
t t K TMR TMR + =
MgO
nom
RA
P
P
t
RA
K
R
R
A =
A
MgO
nom
TMR
nom
RA
AP
AP
t
TMR
K
RA
K
R
R
A
|
|
.
|

\
|
+
+ =
A
1
MTJ Feasible Region
What is the MTJ feasible region in the R
P
-
R
AP
plan given the following:
Desired write current
Desired basic cell area
Column MUX width
Certain technology
Certain variations (Yield)
Matching parameters (Yield)
Dec-2009 Tape-out
IBM-90nm-CMOS
V
WL
= V
DD
= 1 V
I
WR
= 500 A
W
a
=2.56 m
W
P,MUX
=16 m
W
N,MUX
=8 m
MOS K varies +/- 20%
MOS VT varies +/- 50mV
MTJ: RA = 2 .m
2
MTJ: K
RA
= 34 .m
2
/nm
MTJ: TMR = 100%
MTJ: K
TMR
= 200 %/nm
MTJ: t
MgO
= 0.2 A
o
Current Sensing: V
R
= 600 mV
Current Sensing: I
R
= 20 A
0 500 1000 1500 2000
0
200
400
600
800
1000
1200
1400
1600
1800
2000
R
P
(O)
R
A
P

(
O
)
MTJ Feasible Region
SRAM-Area Constraint
IBM-90nm-CMOS
V
WL
= V
DD
= 1 V
I
WR
= 500 A
W
a
=2.56 m
W
P,MUX
=16 m
W
N,MUX
=8 m
MOS K varies +/- 20%
MOS VT varies +/- 50mV
MTJ: RA = 2 .m
2
MTJ: K
RA
= 34 .m
2
/nm
MTJ: TMR = 100%
MTJ: K
TMR
= 200 %/nm
MTJ: t
MgO
= 0.2 A
o
Current Sensing: V
R
= 600 mV
Current Sensing: I
R
= 20 A

Flash-Area Constraint

DRAM-Area Constraint

Area Minimization Problem
Minimize: Effective cell area
Subject to:
MTJ resistances and write current value
MTJ variations
Parallelizing/Anti-parallelizing Write current equations
MOS variations and matching parameters
Speed must come into picture to constrain the
optimum memory partitioning

May be able to formulate this into a standard
optimization problem form that can be solved
efficiently
Remaining Issues
Analyzing Read/Write Speed and adding this as a
constraint in the optimization problem

The same with power

More analysis is needed for the minimum required
sensing signal (current or voltage)
CMOS mismatches and offset
Signal degradation due to MgO thickness variation
Possible signal degradation due to CMOS process variation
(dependant on the SA implementation)

Regenerating all results for different technologies