By R. K. Chaitanya Y. Anil Kumar M.Tech.

,(VLSI)

Overview
Advantages and Disadvantages of SRAM Programming
Building Blocks of SRAM based Architecture Architectures of XC2000 XC3000 XC4000

Basic Terminologies
Pin - a logic cell input or output. Connection - a pair of logic cell pins that are to be electrically

connected. Net - a set of logic cell pins that are to be electrically connected. A net can be divided into one or more connections. Wiring segment - a straight section of wire that is used to form part of a connection. Routing switch - a device that is used to electrically connect two wiring segments. Track - a straight section of wire that spans the entire width or length of a routing channel. A track can be composed of a number of wiring segments of various lengths. Routing channel - the rectangular area that lies between two rows or two columns of logic cells. A routing channel contains a number of tracks.

Xilinx FPGA Structure

Fixed array of

Configurable Logic Blocks (CLBs) connectable by a system of pass transistors, driven by SRAM cells

Advantages and Disadvantages of SRAM Programming

Volatility
External Memory Reprogrammability

Quality
Process Leadership

Basic Building Blocks

1. Look up table
An n-input look up table

implements 2n x 1 memory composed of configurable memory cells. Implements any of the functions of its inputs.

When FPGA is programmed

the memory is loaded with the bit pattern corresponding to the truth table of the function.

Basic Building Blocks(2)

2. Programmable Interconnect Point(PIP)

PIP controls the connection of

wiring segments in the programmable interconnect. Uses a pass transistor whose gate is connected to an SRAM, source and drain are connected between two nodes. 3. Multiplexer Third building block is a multiplexer controlled by a configurable memory cell. Selection lines of the multiplexer can be programmed using SRAM.

The XC2000 CLB

Consists of two 3-input LUTs producing two functions F and G. Two LUTs can be multiplexed to produce any function of four inputs

on both outputs. It includes a single storage element that can be configured as an edge sensitive D-type flip flop or as a level sensitive D-type latch Data input to Flip flop is from LUT function F & Clock input can come from G function or from input C or from separate clock input K.

The XC2000 IO Block

All Chip outputs can be 3-

stated and bidirectional. The three state control can be fixed in the configuration bitstream. So, On chip logic can control the direction of I/O pads. The input signal can be latched in the I/O block, reducing holding times for latched inputs.

The XC2000 Wiring Architecture

Includes 4 horizontal and 5 vertical

general-purpose interconnect segments between switchboxes in the array. The switchbox PIPS connect the segments in pairs. The segments are grouped into the channels in which each segment is part of a track. XC2000 provides repowering buffers in the interconnect to speed up long distance connections. The array of tiles is divided into nine segments in a grid arrangement with general interconnect signals re-powered every time the signal crosses from one section into the next. Local signals within grid are not repowered.

The XC2000 Interconnect

&

Switchbox Connections

The XC2000 Wiring Architecture(2)

Wiring architecture includes direct

connections to horizontally and vertically adjacent blocks. These connections provide high speed dedicated interconnect path to adjacent CLBs through single multiplexer input, avoiding general purpose interconnect. Wiring includes 2- vertical long lines and one horizontal long line. A long line is a single metal segment that spans the entire width or height of the array of tiles bypassing all switchboxes. Signals are buffered onto the long lines. To further support high fan-out, low skew signals, the XC2000 FPGA includes 2 high-drive buffers with dedicated global interconnects to all CLBs.

Block to Interconnect Connections

The connections to the CLB

are distributed around the four sides of the block. Input multiplexers in the figure shown as boxes, appear as independent PIPs to improve the clarity of the drawing The outputs of the CLB can connect to only half the segments in the channel.

The XC2000 Family members

Member CLB Array size Ios Gate Capacity
max Typical

XC2064

8X8

58

1200

800

XC2018

10X10

74

1800

1200

The XC3000 CLB

The XC3000 CLB(2)

Consists of a look-up table that can implement any

function of five variables, any two functions of four variables, and some functions of up to seven variables. The CLB has two outputs, both of which may be either combinational or registered. Less delay penalty. Has two flip flops, to ensure that all combinational logic can be followed by a pipelining flip-flop. Reset and clock signals for the flip flops are driven by separate signals other than input and functions unlike in XC2000 The register rich cells lets the XC3000 implement state intensive applications and heavily pipelined designs efficiently.

The XC3000 IO block

XC3000

consists of an additional flip flop in the output path. By registering data in the I/O block , the clock-to-out the time does not include interconnect delays. XC3000 IOB also includes a programmable pull-up, optional output inversion and selectable slew rate. Input from the pad can be brought into the interior of the chip either directly or registered or both.

The XC3000 Wiring Architecture

XC3000 Wiring architecture

The XC3000 Wiring Architecture(2)

Has five general interconnect lines both vertically and

horizontally. Each CLB has direct connections to adjacent CLBs both vertically and horizontally. The switchbox connections in the XC3000 are more uniform across the segments with the interconnect pattern Since the XC3000 tile was intended to be built into larger arrays than the XC2000, it includes more long interconnect. There are 3-vertical and 2-horizontal long lines. Two of the horizontal long lines are driven by three state buffers along the line. The difficulties of repowering buffers in XC2000 can be overcome using combination of hardware and software.

The XC3000 Wiring

The XC3000 Block to Interconnect Connections

Here the inputs are connected to segments in two

wiring channels. A net routed in either channel can be connected to the input pin, provided it is on the proper track in the channel. Similarly, outputs can be connected to two different channels.

Input PIPS in XC3000

Output PIPS in XC3000

The XC3000 family

The XC4000 CLB

The XC4000 CLB(2)

It Contains 3 LUTs and 2 flip flops. The two primary LUTs F and G each can implement

any function of 4 variables each. The above two functions can be used independently or can be combined with another input in the H LUT to make any function of 5 inputs or some functions of upto 9 inputs. The flip flops can take their inputs independently from the LUTs or from external signals, but they share control signals. Flip flop outputs are not recirculated internally.

The XC4000 CLB(3)

The XC4000 CLB includes dedicated high-speed carry

logic. The dedicated carry logic in the xc4000 substantially speeds up arithmetic while doubling its density. The F & G LUTs can be configured as 16 x 1 static memories. To write into the LUT memory, the LUT inputs address the memory cell to be written. Additional inputs to the CLB are write enable(WE) and data(D). Reading from a memory is same as evaluating a function. One CLB can implement 32bits of memory, configured either as 16 x 2 or 32 x 1.

XC4000 CLB in Arithmetic mode

Here the F & G

LUTs compute two sums while dedicated carry logic calculate the carries.

The XC4000 IO Block

The XC4000 IO Block(2)

Signals to be output from the chip can be registered before

output and enabled by a separate control signal. Outputs can be optionally pulled up or down and the output driver can be configured with either fast or slow slew rate. Inputs from the pad can be brought into the interior of the chip directly, registered or both to facilitate multiplexed bus interfaces. Inputs can drive dedicated decoders, built into the edge interconnect for fast recognition of addresses. It contains boundary scan logic compatible with ANSI IEEE 1149.1 JTAG.

The XC4000 IO Block(3)

Boundary Scan is a Design For Test(DFT) technique in

which the IO cells are configured as a shift register around the periphery of the chip for testing purposes. Boundary Scan check internal logic or external logic. Scan operations can take place before or after the FPGA is programmed and do not interfere with the operations of the part.

The XC4000 Wiring Architecture

The XC4000 Wiring Architecture(2)

The routing resources form a totally symmetric array

of potential connections. The routing wiring includes:

Single length wires intersecting through switch boxes which allows

every horizontal wire to connect to one vertical wire. Double length lines that consist of track segments, each track spanning two CLBs length and it bypass alternate switch boxes.

XC4000 interconnect includes more long and global

lines high speed fanout & high speed wiring. The double length lines allows a signal to travel twice the distance in the same amount of time or to travel half the time because the signal delay is more dependent on the number of PIPS through which a signal passes than on the length of the segments.

The XC4000 Wiring Architecture (3)

To improve routability the long

lines can be broken into two half long lines and thus decreasing the delay also. Two of the long lines in each row can be configured as 3 state buses. Signals on global long lines can originate on chip or off chip and are driven by dedicated high drive clock buffers. They are wired through the core of the chip to all CLBs to minimize clock skew.

The XC4000 Switch Box

The switch box connections are

significantly fewer in XC4000 than those in XC2000 & XC3000. Inside the switch box, each segment can connect to three others, one on each of the other three sides of the switch box. Fewer PIPs results in faster interconnect but wiring may be more difficult. As a result, the XC4000 has more interconnect segments in the channel than equivalent XC3000.

XC4000 has 8 single

length lines, 4 double lines & 6 long lines in each channel horizontally and vertically. It has 4 additional clock lines per column.

The XC4000 Family Members