Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Computer Architecture
CS 215
1
Sequential Circuits
Inputs Outputs
Combinat
ional
Storage Logic
Elements
Storage Next
State State
elements
Latches or
Flip-Flops
Combinatorial
Logic
2
Sequential Circuits
Inputs Outputs
Combinat
ional
Storage Logic
Elements
Combinatorial Logic Next
Next state function
Next State = f(Inputs, State State
State)
Output function
(Mealy)
Outputs = g(Inputs,
State)
Output function
(Moore)
Outputs = h(State)
Output function type
depends on specification
and affects the design
significantly
3
Sequential Circuits
Synchronous
Behavior defined from knowledge of its signals at discrete
instances of time
Storage elements observe inputs and can change state
only in relation to a timing signal (clock pulses from a
clock)
Asynchronous
Behavior defined from knowledge of inputs an any instant
of time and the order in continuous time in which inputs
change
If clock just regarded as another input, all circuits are
asynchronous!
Nevertheless, the synchronous abstraction makes
complex designs tractable!
4
Discrete Event Simulation
Rules:
Gates modeled by an ideal (instantaneous)
function and a fixed gate delay
Any change in input values is evaluated to
see if it causes a change in output value
Changes in output values are scheduled for
the fixed gate delay after the input change
At the time for a scheduled output change,
the output value is changed along with any
inputs it drives
5
Simulated NAND Gate
F(Instantaneous) Example: A 2-Input
A NAND gate with a 0.5
DELAY 0.5 ns. F ns. delay
B
Assume A and B have
been 1 for a long time
At time t=0, A
changes back to 1. to
a 0 at t= 0.8 ns,
t (ns) A B F(I) F Comment
–∞ 1 1 0 0 A=B=1 for a long time
0 1⇒ 0 1 1⇐ 0 0 F(I) changes to 1
0.5 0 1 1 1 ⇐ 0 F changes to 1 after a 0.5 ns delay
0.8 1 ⇐ 0 1 1⇒ 0 1 F(Instantaneous) changes to 0
0.13 1 1 0 1 ⇒ 0 F changes to 0 after a 0.5 ns delay
6
Basic (NAND) S–R Latch
S (set)
“Cross-Coupling” Q
two NAND
gates gives
R (reset) Q
the S-R Latch
S = 0, R = 0 is Time R S Q Q Comment
forbidden as
input pattern 1 1 ? ? Stored state unknown
1 0 1 0 “Set” Q to 1
1 1 1 0 Now Q “remembers” 1
0 1 0 1 “Reset” Q to 0
1 1 0 1 Now Q “remembers” 0
0 0 1 1 Both go high
1 1 ? ? Unstable!
7
Basic (NOR) S–R Latch
R (reset)
Cross- Q
coupling
two
NOR S (set) Q
gates
gives Time R S Q Q Comment
the 0 0 ? ? Stored state unknown
S–R 0 1 1 0 “Set” Q to 1
0 0 1 0 Now Q “remembers” 1
Latch
1 0 0 1 “Reset” Q to 0
0 0 0 1 Now Q “remembers” 0
1 1 0 0 Both go low
0 0 ? ? Unstable!
8
Clocked S-R Latch
Adding two NAND S
gates to the basic Q
S-R NAND latch
C
gives the clocked
S–R latch: Q
R
Has a time sequence behavior similar to the
basic S-R latch except that the S and R inputs are
only observed when the line C is high.
C means “control” or “clock”.
9
Clocked S-R Latch
The Clocked S-R Latch can be described by a table
S
Q Q(t) S R Q(t+1 ) Comment
C 1 1 1 1 No change
1 1 1 1 Clear Q
Q
R 1 1 1 1 Set Q
The table describes 1 1 1 ??? Indeterminate
what happens after the 1 1 1 1 No change
clock [at time (t+1)] 1 1 1 1 Clear Q
based on: 1 1 1 1 Set Q
current inputs (S,R) and 1 1 1 ??? Indeterminate
current state Q(t).
10
D Latch
D
Q
Adding an inverter
to the S-R Latch, C
gives the D Latch: Q
Note that there are
no “indeterminate”
The graphic symbol for a
states!
D Latch is:
Q D Q(t+1) Comment
D Q
0 0 0 No change
0 1 1 Set Q
1 0 0 Clear Q C Q
1 1 1 No Change
11
Flip-Flops
Master-slave flip-flop
Edge-triggered flip-flop
Standard symbols for storage
elements
12
S-R Master-Slave Flip-Flop
S S Q S Q
Two clocked Q
C C C
S-R latches in series
with the clock on the R R Q R Q
Q
second latch inverted
The input is observed
by the first latch with C = 1
The output is changed by the second latch with C = 0
The path from input to output is broken by the
difference in clocking values (C = 1 and C = 0).
The behavior demonstrated by the example with D
driven by Y given previously is prevented since the
clock must change from 1 to 0 before a change in Y
based on D can occur.
13
Edge-Triggered D Flip-Flop
D D Q S Q
The edge-triggered Q
D flip-flop is the C
same as the master-
C C Q
slave D flip-flop R Q Q
14
Positive-Edge Triggered D
Flip-Flop
Formed by
D D Q S Q Q
adding inverter
to clock input
C
C C Q R Q Q
Q changes to the value on D applied at the positive clock edge within timing constraints to be specified
Our choice as the standard flip-flop for most sequential circuits
15
Standard Symbols for
Storage Elements S S D D
R R C C
SR SR D with 0 Control
D with 1 Control
(a) Latches
Master-Slave:
Postponed outputS S D D
indicators C C
R R C C
Dynamic D D
indicator
C C
Triggered D Triggered D
(c) Edge-Triggered Flip-Flops 16
State Diagrams
The sequential circuit function can be
represented in graphical form as a state
diagram with the following components:
A circle with the state name in it for each state
A directed arc from the Present State to the Next
State for each state transition
A label on each directed arc with the Input values
which causes the state transition, and
A label:
On each circle with the output value produced, or
On each directed arc with the output value
produced.
17
State Diagrams
Label form:
On circle with output included:
state/output
Moore type output depends only on state
On directed arc with the output
included:
input/output
Mealy type output depends on state and
input
18
Other Flip-Flop Types
J-K and T flip-flops
Behavior
Implementation
Basic descriptors for understanding and
using different flip-flop types
Characteristic tables
Characteristic equations
Excitation tables
19
J-K Flip-flop
Behavior
Same as S-R flip-flop with J analogous to S
and K analogous to R
Except that J = K = 1 is allowed, and
For J = K = 1, the flip-flop changes to the
opposite state
As a master-slave, has same “1s catching”
behavior as S-R flip-flop
If the master changes to the wrong state,
that state will be passed to the slave
E.g., if master falsely set by J = 1, K = 1 cannot
reset it during the current clock cycle
20
J-K Flip-flop Symbol
Implementation
To avoid 1s catching
behavior, one solution
used is to use an J
edge-triggered D as
the core of the flip-flop
C
K
J D
K
C
21
T Flip-flop
Behavior
Has a single input T
For T = 0, no change to state
For T = 1, changes to opposite state
22
T Flip-flop Symbol
Implementation
To avoid 1s catching
T
D
T
C
23
Basic Flip-Flop Descriptors
Used in analysis
Characteristic table - defines the next state
of the flip-flop in terms of flip-flop inputs and
current state
Characteristic equation - defines the next
state of the flip-flop as a Boolean function of
the flip-flop inputs and the current state
Used in design
Excitation table - defines the flip-flop input
variable values as function of the current
state and next state
24
D Flip-Flop Descriptors
Characteristic Table
D Q(t+1) Operation
0 0 Reset
1 1 Set
Characteristic Equation
Q(t+1) = D
Excitation Table
Q(t+1) D Operation
0 0 Reset
1 1 Set
25
T Flip-Flop Descriptors
Characteristic Table
T Q(t+1) Operation
0 Q(t) No change
1 Q(t) Complement
Characteristic Equation
Q(t+1) = T ⊕ Q
Excitation Table
Q(t 1) T Operation
+
Q(t) 0 No change
Q(t) 1 Complement
26
S-R Flip-Flop Descriptors
Characteristic Table S R Q(t+1) Operation
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 ? Undefined
Characteristic Equation
Q(t+1) = S + R Q, S.R = 0
Excitation Table Q(t) Q(t+1) S R Operation
0 0 0 X No change
0 1 1 0 Set
1 0 0 1 Reset
1 1 X 0 No change
27
J-K Flip-Flop Descriptors
Characteristic Table J K Q(t+1) Operation
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q(t) Complement
Characteristic Equation
Q(t+1) = J Q + K Q
Excitation Table Q(t) Q(t+1) J K Operation
0 0 0 X No change
0 1 1 X Set
1 0 X 1 Reset
1 1 X 0 No Change
28