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3/11/2014
Outline
Problems with sequential testing What is scan Types of scan Types of storage devices Scan Architectures Cost of Scan Partial Scan
Timing problems
SFF
SFF
TC or TCK SCANIN
Connect the SFF in a shift register and test them Test the combinational part
Testing strategy
Principle of scan path
Each input to the FF is considered an output of the combinatorial circuit each output of the FF is an input to the circuit
Testing strategy
Example: A realization for the double-throw switch
End repeat.
An Example
Combinational Circuit
y2 F G1 F y1 G2 G3 Z
D 1 Clk
Y1
D 2 Clk
Y2
Clk
Clk
Scan-in
Level-sensitive Latch
The latch works with the 3 phases A, B and C
For normal operation, clocks B and C For shift operation, clocks B and A
D C
SCAN-IN
L1
L1
L2 B (b)
L2
L1
C Scan-in B
L2
L2 B (a) (b)
L2
MCK SCK SD
Logic overhead
Q D flip-flop Normal mode Scan mode t MCK TCK MCK TCK SCK
TCK
LSSD: Testing
Repeat until all patterns are applied.
a. Apply a pattern at the primary inputs. b. Clock C; then clock B once and observe the results at the primary outputs. c. Shift out the response Apply the initialization for the next pattern at SI. Clock A, then clock B, M times. Observe at the primary outputs and the SO pins.
M U X
SFF
TC CK
Scan Overhead
IO pins: One pin necessary. Area overhead:
Gate overhead = [4 nff/(ng+10nff)] x 100%, where ng = comb. gates; nff = flip-flops;
Example ng = 100k gates, nff = 2k flip-flops, overhead = 6.7%.
More accurate estimate must consider scan wiring and layout area.
Performance overhead:
Multiplexer delay added in combinational path; approx. two gate-delays. Flip-flop output loading due to one additional fanout; approx. 5-6%.
Hierarchical Scan
Scan flip-flops are chained within subnetworks before chaining subnetworks. Advantages:
Automatic scan insertion in netlist Circuit hierarchy preserved helps in debugging and design changes
Hierarchical netlist
Flat layout
None
Hierarchical Optimum layout
0.0
16.93% 11.90%
1.00
0.87 0.91
Develop design
Scan hardware insertion
Develop test
Scan netlist
Chip layout: Scanchain optimization, timing verification
Test program
Mask data
Scan Summary
Scan is the most popular DFT technique:
Rule-based design Automated DFT hardware insertion Combinational ATPG
Advantages:
Design automation High fault coverage; helpful in diagnosis Hierarchical scan-testable modules are easily combined into large scan-testable systems Moderate area (~10%) and speed (~5%) overhead
Disadvantages:
Large test data volume and long test time Basically a slow speed (DC) test
Partial-scan architecture
Scan flip-flop selection methods Cyclic and acyclic structures Partial-scan by cycle-breaking Scan variations Scan-hold flip-flop (SHFF) Summary
Partial-Scan Definition
A subset of flip-flops is scanned. Objectives:
Minimize area overhead and scan sequence length, yet achieve required fault coverage Exclude selected flip-flops from scan:
Improve performance Allow limited scan design rule violations
Allow automation:
In scan flip-flop selection In test generation
Partial-Scan Architecture
PI Combinational circuit PO
TC
SFF SCANIN
Structure based:
Cycle breaking Balanced structure
Sometimes requires high scan percentage
ATPG based:
Use of combinational and sequential TG
Cycle Breaking
Difficulties in ATPG S-graph construction and MFVS problem Test generation and test statistics Partial vs. full scan Partial-scan flip-flop
Benchmark Circuits
Circuit PI PO FF Gates Structure Sequential depth Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s1196 14 14 18 529 Cycle-free 4 1242 1239 0 3 0 99.8 100.0 3 313 10 s1238 14 14 18 508 Cycle-free 4 1355 1283 0 72 0 94.7 100.0 3 308 15 s1488 8 19 6 653 Cyclic -1486 1384 2 26 76 93.1 94.8 24 525 19941 s1494 8 19 6 647 Cyclic -1506 1379 2 30 97 91.6 93.4 28 559 19183
Relevant Results
Theorem 8.1: A cycle-free circuit is always initializable. It is also initializable in the presence of any non-flip-flop fault. Theorem 8.2: Any non-flip-flop fault in a cyclefree circuit can be detected by at most dseq + 1 vectors (dseq is the sequential depth). ATPG complexity: To determine that a fault is untestable in a cyclic circuit, an ATPG program using nine-valued logic may have to analyze 9Nff time-frames, where Nff is the number of flipflops in the circuit.
Cycle-Free Example
Circuit
F2 2 F1 Level = 1 F2 2 F1 Level = 1 F3 3 dseq = 3 F3 3
s - graph
A Partial-Scan Method
Select a minimal set of flip-flops for scan to eliminate all cycles. Alternatively, to keep the overhead low only long cycles may be eliminated. In some circuits with a large number of selfloops, all cycles other than self-loops may be eliminated.
Test Generation
Scan and non-scan flip-flops are controlled from separate clock PIs:
Normal mode Both clocks active Scan mode Only scan clock active
0
4 9
4
2 1
14
10 5
1,247
157 32
61
11 4
89.01%
95.90% 99.20%
805
247 136
805
1,249 1,382
10
21
1
0
3
0
13
2
4
2
100.00%
100.00%
112
52
1,256
1,190
Partial-scan
2,781 149 30 2.63% 4,603 65/79 93.7% 99.5% 727 s 1,117 34,691
Full-scan
2,781 0
179 15.66% 4,603 214/228 99.1% 100.0% 5s
0
0.0% 4,603 35/49 70.0% 70.9% 5,533 s 414 414
585 105,662
MUX
SD TC CK TC
Master latch
Slave latch
CK
Normal mode Scan mode
Scan Variations
Integrated and Isolated scan methods
Scan path: NEC 1968 Serial scan: 1973 LSSD: IBM 1977 Scan set: Univac 1977 RAS: Fujitsu/Amdahl 1980
PO
nff
bits SCANOUT SEL
Address decoder
ADDRESS ACK Address scan register log2 nff bits
D
SD Scan flip-flop (SFF)
To comb. logic
CK
TC SCANOUT
SEL
RAS Applications
Logic test:
reduced test length.
Delay test:
Easy to generate single-input-change (SIC) delay tests.
Advantage:
RAS may be suitable for certain architecture, e.g., where memory is implemented as a RAM block.
Disadvantages:
Not suitable for random logic architecture High overhead gates added to SFF, address decoder, address register, extra pins and routing
SD
TC CK SFF
HOLD
The control input HOLD keeps the output steady at previous state of flip-flop. Applications:
Reduce power dissipation during scan Isolate asynchronous parts during scan test Delay testing