Digital Electronics

MEMORY

Memory

Memory is required to store:

1. data 2. application programs 3. operating system

ECE 301 - Digital Electronics

Memory

Can be broadly classified as:

Random Access Memory (RAM) or Read Only Memory (ROM)

ECE 301 - Digital Electronics

Random Access Memory (RAM)

Can be written to or read from.

Read/Write memory

Reading from RAM is non-destructive. Access time to read from any memory location is the same.

As compared to serial access memory. Information is lost when power is removed.

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Volatile

Random Access Memory (RAM)

ECE 301 - Digital Electronics

Random Access Memory (RAM)

Static Random Access Memory (SRAM)

Based on the Flip-Flop Requires a large number of transistors Fast Uses a single transistor to store charge Requires very few transistors Must be periodically refreshed Slow(er)
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Dynamic Random Access Memory (DRAM)

Read Only Memory (ROM)

Can only be read from. Memory is written (or programmed) once Reading from ROM is non-destructive. Access time to read from any memory location is the same.

As compared to serial access memory. Information is retained even after power is removed.
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Non-Volatile

Read Only Memory (ROM)

ECE 301 - Digital Electronics

Read Only Memory (ROM)

Programmable Read Only Memory (PROM)

Can be programmed Can be programmed and erased Can be erased using an electrical signal Can be erased using Ultraviolet light
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Erasable PROM (EPROM)

Electrically Erasable PROM (EEPROM)

UV Erasable PROM (UVEPROM)

Read Only Memory (ROM)

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Memory

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Memory

Random Access Memory

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Random Access Memory

Address

Location in memory of the binary information Must be decoded to select the appropriate location and read/write the associated data k-bit address 2k memory locations Binary information of interest

Data

Stored in a specific location in the memory

Typically organized into words Each word has n bits
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Random Access Memory

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 A memory unit is a collection of storage cells with associated circuits needed to transfer information in and out of the memory device.

The n data input lines provide the information to be stored in memory and the n data output lines supply the information out of memory. The k address lines specify the particular word chosen among the many available memory locations. The 2 control signals write and read are used to transfer the data into the memory and read data from memory.

 The memory unit is specified by the number of words it contains and the number of bits in each word. Address line is used to select one particular word.
Each word in memory is assigned an identification number called address, starting from 0 upto 2k-1. (k- no. of bits in the address lines)

Block diagram of 1024X16 memory

address

data

10-bit address 1024 locations

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 A decoder accepts the address lines (A9, A8,A1, A0) and provides the paths needed to select the word specified. The memory size varies from 1024 words requiring an address of 210 bits to 232 words, requiring 32 bit address bits.
These memory size are represented using letter symbol K (kilo-210), M (Mega - 220), and G (giga 230).

 Consider for example the memory unit with a capacity as shown in fig. Since 1 K = 1024 = 210 and 16 bits constitute 2 bytes and the possible content of the first three and last 2 words of this memory, each word contains 16 bits that can be divided into 2 bytes.

The words are recognized by their decimal address from 0 to 1023.

The equivalent binary address consists of 10 bits.

 The no. of bits in the address is determined from the relationship 2k>m.

where m is the total no of words and k is the number of address bits needed to satisfy the relationship.

WRITE OPERATION: The write signal is used to write the data into the specified memory location. Steps to be followed to write the data: Apply the binary address of the desired word to the address lines Apply the data bits that must be stored in memory to the data input lines Activate the write input.

READ OPERATION:
Steps to be followed:

Apply the binary address of the desired word to the address lines
Activate the read input. Now the required data is available in the data line.

Control inputs of memory chip

The memory enable (chip select) is used to enable the particular memory in a multichip implementation of a large memory. When the memory enable is inactive, the memory chip is not selected and no operation is performed. When the memory enable input is active, the read/write input determines the operation to be performed as shown in table.

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Timing waveform
The operation of the memory unit is controlled by an external device such as central processing unit (CPU). The CPU is synchronized by its own clock but the memory does not employ an internal clock.

Instead, its read and write operations are specified by cycle time of a memory .(Cycle time : is the time required to complete a write operations)

 The CPU must provide the memory control signals in such a way as to synchronize its internal operations with the read and write operation of a memory. This means that the access time and cycle time of the memory must be within a time equal to a fined number of CPU clock cycles

Write Cycle

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Read Cycle

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Basic construction of binary cell

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General structure of 4X4 RAM

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RAM - Types
(I) Static RAM Bipolar RAM MOSFET RAM MOSFET RAM

(II) Dynamic RAM

Static RAM
Logic Diagram:

Bipolar SRAM cell

MOSFET RAM cell

256x4 static RAM

Dynamic RAM cell

Writing 1 into the memory cell

Reading 1 from the memory cell

Refreshing a stored 1

ROM (Read Only Memory)

Masked ROM Programmed ROM (PROM) Erasable PROM (EPROM) UV EPROM Electrically Erasable PROM(EEPROM)

ROM Organization

PROM

Bipolar PROM cell

PROM using MOSFET

Fuse Technologies

EPROM

UV EPROM

EEPROM

PROGAMMABLE LOGIC DEVICES(PLD)

Symbology of PLD

PROGRAMMABLE LOGIC ARRAY (PLA)

FIELD PROGRAMMABLE GATE ARRAY (FPGA)

FPGA MODULE

Design Procedure
Capture the logic circuit to be implemented with a suitable software package. Functional simulation simulates the circuit to determine whether it is function properly.

Configure and interconnect the modules of the FPGA to produce the desired logic circuit.this may be done automatically by a routing software called routers.

 Programming is done by the FPGA interconnection. After programming it must be tested. If the designed function is not fulfilled it must be reprogrammed.