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Manufacturing problems
Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.
Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR
Transistor problems
Wiring problems
Diffusion: changes in doping -> variations in resistance, capacitance. Poly, metal: variations in height, width -> variations in resistance, capacitance. Shorts and opens:
Oxide problems
Variations in height. Lack of planarity -> step coverage.
metal 2 metal 2 metal 1
Via problems
Via may not be cut all the way through. Undersize via has too much resistance. Via may be too large and create short.
Designed to scale across a wide range of technologies. Designed to support multiple vendors. Designed for educational use. Fairly conservative. http://www.mosis.com/design/rules/
The standard CMOS technology accessed by MOSIS is a single polysilicon, double metal, bulk CMOS process with enhancement-mode n-MOSFET and p-MOSFET devices.
Copyright 1998, 2002 Prentice Hall PTR
Wires
All wire widths are multiples of
6 metal 3
3
3
metal 2
metal 1
3
2
Modern VLSI Design 3e: Chapter 2
pdiff/ndiff
poly
Copyright 1998, 2002 Prentice Hall PTR
Transistors
poly 3 2 2 3 1
diffusion
substrate
Vias
Metal 3 via
Type: metal3/metal2. Rules:
Tub tie
4 1
Spacing
diffusion/diffusion: 3 poly/poly: 2 poly/diffusion: 1 via/via: 2 metal1/metal1: 3 metal2/metal2: 4 metal3/metal3: 4
Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR
Overglass
Cut in passivation layer. Minimum bonding pad: 100 m. Pad overlap of glass opening: 6 Minimum pad spacing to unrelated metal2 or metal3: 30 Minimum pad spacing to unrelated metal1, poly, active: 15
Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR