1

PULSE CODE MODULATION (PCM)

DEFINITION: Pulse code modulation (PCM) is essentially analog-
to-digital conversion of a special type where the information
contained in the instantaneous samples of an analog signal is
represented by digital words in a serial bit stream.
Basic Steps For PCM System
Limiter
Filtering
Sampling
Quantization
Encoding
Line Coding
FILTERING Filters are used to limit the speech signal to the
frequency band 300-3400 Hz.

Analog to Digital Conversion
The Analog-to-digital Converter (ADC)
performs three functions:
Sampling
Makes the signal discrete in time.
If the analog input has a bandwidth
of W Hz, then the minimum sample
frequency such that the signal can
be reconstructed without distortion.
Quantization
Makes the signal discrete in
amplitude.
Round off to one of q discrete levels.
Encode
Maps the quantized values to digital
words that are 8 bits long.
If the (Nyquist) Sampling Theorem is
satisfied, then only quantization introduces
distortion to the system.
ADC
Sample
Quantize
Analog
Input
Signal
Encode
111
110
101
100
011
010
001
000
Digital Output
Signal
111 111 001 010 011 111 011
4
SAMPLING PROCESS
5
4.3 Sampling Theorem
X
Digital signal
s(t)
m
s
(t) m(t)
m(t)
t
m
s
(t)
t
s(t)
t
T
s
Sampling theorem states that :"If a band limited
signal is sampled at regular intervals of time and
at a rate equal to or more than twice the highest
signal frequency in the band, then the sample
contains all the information of the original
signal."
fS 2fm
Fourier series for impulse train :


6
S(t) = T
S
+ 2T
S
(Cos 2 (t T
S
)+ Cos 2x2 (t T
S
+.)
SAMPLING & COMBINING CHANNELS
7
PAM OUTPUT SIGNALS
8
RECONSTRUCTION OF ORIGINAL SIGNAL
9
f
3f

2
s
2f
s
3f
s
f
s 0
f
s
-f
m
f
s
+f
m 2f
s
+f
m
3f
s
+f
m
3f
s
-f
m
2f
s
-f
m
m
s
(f)
Spectrum of the sampled signal
The spectrum of the sampled signal has sidebands f
s
f
m
, 2f
s
f
m
, 3f
s
f
m
and so
on.
10
The choice of sampling frequency, f
s
must follow the sampling theorem to overcome
the problem of aliasing and loss of information
(a) Sampling frequency=> f
s1
<2f
m (max)
f
2f
s1
3f
s1
f
s1
f
m
Aliasing
m
s
(f)
(b) Sampling frequency=> f
s2
>2f
m (max)
f
2f
s2
3f
s2
f
s2
f
m
m
s
(f)
Shannon sampling
theorem=>f
s
2f
m

Nyquist frequency
f
s
=2f
m
=f
N
A bandlimited signal that
has a maximum
frequency, f
max
can be
regenerated from the
sampled signal if it is
sampled at a rate of at
least 2f
max .

11
Pulse Code Modulation (PCM)

Codec technique
Voice Bandwidth =
300 Hz to 3400 Hz
Sampling Stage Analog Audio Source
= Sample
8 kHz (8,000 Samples/Sec)
Nyquists Theorem says
sample at twice the bandwidth of
the line.
Voice bandwidth ~ 3400 Hz.
So, must sampling rate should be
6800 samples/sec.
PCM actually uses 8000
samples/sec since cutoff not
sharp.
Height of sampled signal above /
below the base line is converted
to a binary value
12
4.4 Detection of Sampled Signal
By using LPF to the sampled signal, m
s
(t)
LPF m
s
(t) m(t)
Cut-off frequency , f
o
for LPF must be within the range: f
m
f
o
f
s
- f
m
Eventhough the sampled signal can be detected easily at f
s
=2f
m ,
but usually
f
s
>2f
m
. The main reason is to have a guardband .

Therefore, the maximum frequency that can be processed by the sampled
data using sampling frequency, f
s
(without aliasing) is:
=>f
m
= f
s
/ 2 =1 / 2T
s
13
4.3.1 Difference in Sampling Methods
In every sampling methods, the pulse amplitude is directly proportional to the
amplitude of the information signal
Practically, an ideal sampling is difficult to generate
However, by using an ideal and natural sampling, noise can be eliminated, which
is not the case for flat-top sampling
I deal Sampling Flat-top Sampling
m
s
(t)
t
Natural Sampling
14
Natural Sampling Flat-top Sampling
Information signal
Pulse signal
Sampled signal (PAM)
t
m(t)
t
s(t)
T
s

t
m
s
(t)
T
s

t
m
s
(t)
T
s

15
16
PULSE AMPLITUDE MODULATED SIGNAL
NATURAL TOP
SAMPLING
CLOCK
The FET is the switch used as a sampling gate.

When the FET is on, the analog voltage is shorted to ground; when off,
the FET is essentially open, so that the analog signal sample appears at
the output.

Op-amp 1 is a noninverting amplifier that isolates the analog input
channel from the switching function.
17
FLAT-TOP SAMPLING
SAMPLED & HOLD CIRCUIT
HIGH FANOUT
OP
AMP-2
clock

As seen in Figure, the instantaneous amplitude
of the analog (voice) signal is held as a constant
charge on a capacitor for the duration of the
sampling period T
s
.
Op-amp 2 is a high input-impedance voltage
follower capable of driving low-impedance loads
(high fanout).
The resistor R is used to limit the output current
of op-amp 1 when the FET is on and provides
a voltage division with r
d
of the FET. (r
d
, the
drain-to-source resistance, is low but not zero)
sample-and-hold circuit.
Eeng 360 19
Quantization
The output of a sampler is still continuous in amplitude.
Each sample can take on any value e.g. 3.752, 0.001, etc.
The number of possible values is infinite.
To transmit as a digital signal we must restrict the number of
possible values.
Quantization is the process of rounding off a sample according to
some rule.
E.g. suppose we must round to the nearest tenth, then:
3.752 --> 3.8 0.001 --> 0

QUANTIZING-POSITIVE SIGNAL
20
QUANTIZING - SIGNAL WITH + Ve & - Ve VALUES
21
Quantization Interval
Represent the voltage value for each quantized level
For example: For a sampled signal that has 5V amplitude, V
pp

= 10 V divide by the quantized level, L

= 8 level,
Therefore, quantized interval , qi=10V/8=1.25V
Quantization level, L = 2
n
Quantization level depends on the number of binary bits, n
used to represent each sample.
For example:For = 3; Quantization level, L = 2
3
= 8 level.
In this example, first level (level 0) is represented by 000,
whereas bit 111 represents the eigth level
3 terms that are commonly used in the quantization
process:
22
Quantization value, V
k

The middle voltage for each quantized level
For example: for n = 3, quantized level, L

= 8 and a sampled
sinusoidal signal with +5 V ,
The middle quantized value for level 0,
V = - 5V+(1.25V2) = - 4.375V

In this example, for a sample that is in level 0 segment will
be represented by bit 000 with a voltage value of 4.375 V.
The difference between the sampled value and the
quantized value results in quantization noise.
23
For voice communication 256 levels are commonly
used (i.e n = 8)
Quantization
1. Quantizing operation approximates the analog
values by using a finite number of levels. This
operation is considered in 3 steps
a) Uniform Quantizer
b) Quantization Error
c) Quantized PAM signal output
2. PCM signal is obtained from the quantized PAM
signal by encoding each quantized sample value
into a digital word.
Uniform Quantization
Most ADCs use uniform
quantizers.
The quantization levels of a
uniform quantizer are
equally spaced apart.
Uniform quantizers are
optimal when the input
distribution is uniform.
When all values within the
Dynamic Range of the
quantizer are equally likely.
Input sample X
Example: Uniform 3 bit quantizer
q=8 and X
Q
= {1,3,5,7}
2 4 6 8
1
5
3
Output sample
X
Q

-2 -4 -6 -8
Dynamic Range:
(-8, 8)
7
-7
-3
-5
-1
Quantization Characteristic
t
Level 0 : 000
Level 1 : 001
Level 2 : 010
Level 3 : 011
Level 4 : 100
Level 5 : 101
Level 6 : 110
Leve l 7 : 111
1.9V
+5.0V
-5.0V
4.375V
3.125V
1.875V
0.625V
-0.625V
-1.875V
-3.125V
-4.375V
4.3V
1.9V
-3.2V
-4.5V
Quantization level &
binary representation
Quantized
value
Sampled signal
UNIFORM QUANTIZATION
Uniform quantization is a quantization process with a uniform (fixed) quantization
interval.
Example : n = 3 , L

= 8 , signal +5 V ; => V
k
= 1.25 V . Bit rate: f
b
= n
f
s

26
Quantization error
30
Input voltage range: 14 mV to
+14 mV

Binary
number

Input voltage
range (mV)

1 11

10 to 14

1 10

6 to 10

1 01

2 to 6

1 00

0 to 2

0 00

-2 to 0

0 01

-6 to -2

0 10

-10 to -6

0 11

-14 to -10

Example : Uniform Quantization error
Q
n
= LSB voltage /2 = q
i
/2
14 mV = 28 mV with 8 steps and 8 codes.
Therefore Q
n
= 28/8 = 3.5 mV.
Therefore : Q
n
= 3.5 mV / 2 = 1.75 mV
SNR
q
= [1.76 + 6.02n] dB
Noise from quantization error
can be reduced by increasing
the quantization level i.e
increase n.
31
Companding
32
Pulse Code Modulation - Analog to Digital Conversion
Stage 1
Quantizing Stage
Output

100100111011001
A-Law (Europe)
-Law (USAJapan)
33
2 Popular companding system (standardized by ITU)
EUROPE => A - Law
USA/NORTH AMERICA => - Law
A
x for
x
A
for
A
Ax
A
Ax
y
1
0
1
1
log 1
log 1
) log( 1
( (
( (

+
+
+
=
A - compressor paramater. Usually the
value of A is 87.6.
34
USA/NORTH AMERICA => - Law
Law is a standard compress-
expand that is used in America and
Japan. The value of used is 255 (8
bit).
( )

+
+
=
1 log
) 1 log( x
y
(max) i
i
E
E
x =
(max) o
o
E
E
y =
For both laws, the values of x and y
refers to the equation below:
35
ENCODING
CURVE WITH
COMPRESSION
8 BIT CODE
36
P A B C W X Y Z
Sign bit SEGMENT
1 FOR POSITIVE &
0 FOR NEATIVE

0 0 0 0 0 0 0
1 1 1 1 1 1 1
ITU-T Rec. G.704
E1 CAS Transmission Format
Time Slot 16 : Frames 2 through 15 are the same as frame 1
Time Slot 0: Even number frames 2 through 14 are the same as frame 0
Time Slot 0: Odd number frames 3 through 15 are the same as frame 1

1 = bit set to 1 0 = bit set to 0
1/0 = speech / signalling (varying data) X = unassigned bit (normally set to 1)

Fr. Ch. Ch.


1 1 16
2 2 17
3 3 18
: : :
15 15 30

1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Multiframe (16 frames)
Frame 0 (32 Time Slots)
1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Frame 1 (32 Time Slots)
1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Time Slot 0
(8 bits)
0 X 0 1 1 0 1 1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Time Slot 1
Speech (Ch. 1)
Time Slot 16
(8 bits)
0 0 0 0 X 0 X X
Time Slot 0
(8 bits)
1 X 0 X X X X X
Time Slot 16
Signalling Bits
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Speech
Ch. 1-15
Speech
Ch. 16-30
Speech
Ch. 1-15
Speech
Ch. 16-30
Frame
Time Slot
Frame
Alignment
Word
Multi-
Frame
Alignment
Word
Changes to 1 on
loss of distant
multiframe
Changes to 1 on
loss of distant frame
(remote alarm)
Not-Frame
alignment word
A B C D A B C D
LSB
Applying this framing method to the Omniplexer.
TS 0 is used for framing and alarm information
TS 16 contains the voice signalling bits:
the A bit is used for the call status indication.
the B bit is used as a busy indication.
bit C & D are not used in most voice applications.
The Omniplexer assigns channel numbers 1 to 30, for usable transmission.
ITU-T G.704 (32 Time Slots)
1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Omniplexer - 30 Channel Assignments
1 - 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26 27 28 29 30
E1 CAS Transmission Format
E1 CCS Transmission Format
Applying this framing method to the OMNIBranch and OMNIFlex.
TS 0 is used for framing and alarm information
The OMNIBranch assigns channel numbers 1 to 31, for usable transmission.
CCITT G.704 (32 Time Slots)
1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31
OMNIBranch / OMNIFlex - 31 Time Slot Assignments
1 - 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Frame (32 Time Slots)
1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Speech
Ch. 1-31
Time Slot
Time Slot 0
(8 bits)
0 X 0 1 1 0 1 1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Time Slot 1
Speech (Ch. 1)
Frame
Alignment
Word
ITU-T Rec. G.704
Example : PCM-TDM CEPT System
Frame structure and Timing : European standard PCM system : E Line
(a) bits per time slot (b) time slots per frame (c) frames per multiframe
488 ns
3.9 s
3.9 s
125 s
125 s
2 ms
8 bits per
time slot
Bit duration
30 signal + 2 control = 32 channels = 1 frame
Signalling & synchronization
16 frames = 1 multiframe
Duration of multiframe
41
PCM30 basic frame
1 2 3 4 5 6 7 8
X 1
Y Y Y
1

1

1

Bit No.
Value
Message
ca. 3,9 s
1 2 3 4 5 6 7 8
Bit numbering
32 x 8 = 256 bit
125 s
t
voice
1
voice
2
voice
15
voice
16
voice
30
0 1 2 15 16 17 31
SIG
1 2 3 4 5 6 7 8
0 0 1 1 0 1 1
Bit No.
value
Frame alignment
X
PDH E1 signal
42
Bit 1 X Used in international connections
Bit 3 Y=1 FRAME SYNCHRONISATION
Bit 4 Y=1 HIGH ERROR DENSITY
Bit 3,4,5 111 Urgent alarm
Bit 6-8 111 Reserved for national options
Bit 1, X Used in
international
connections,
FAW :-0011011

Frame structure and timing
Number of channel = 32
Number of bits in one time slot = 8
32 channels = 1 frame
Number of bits in a frame = 32 x 8 = 256 bits
PCM 32 channels (30 signals + 2 control)
This frame must be transmitted within the sampling period and thus 8
x 10
3
frames are transmitted per second.
Therefore :
Transmission rate = 8 x 10
3
x 256 = 2.048 Mb/s
Bit duration = 1 / 2.048 x 10
6
= 488 ns
Duration of a time slot = 8 x 488 ns = 3.9 s
Duration of a frame = 32 x 3.9 s = 125 s => (= 1 / 8 kHz = 125 s)
Duration of a multi frame = 16 x 125 s = 2 ms
43
Europe bit rate(Mb/s)

2.048

8.448

34.368

139.264

565.148

Telephone
channel
30

120

480

1920

7680

SDH

2.5Gb/s

Telephone
channel

North America bit
rate(Mb/s)
24

1.544

48

3.152

96

6.321

672

44.736

4032

274.176

Bit rate for PCM & Higher Order Mux
European standard : A-Law
30 + 2 control channel = 32
Bit rate= 32 x 8 bit/sample x 8000 sample/s
= 2.048 Mb/s
North American standard (NAS) : -Law
For every 24 sample, 1 bit is added for
synchronization
For 24 sample => 24 x 8 bit/sample + 1 bit
= 193 bits
Bit rate= 193 x 8000 = 1.544 Mb/s
Needs Multiplexing Process of transmitting two or more
signals simultaneously
44
LINE CODE
AMI CODE SPECTRUM
45
LINE CODE
30 CHL PCM HDB-3 (HIGH-DENSITY BIPLOAR code)
Number of' 1 's preceding
violation is ODD
46












Number of' 1 's preceding
violation is EVEN
Number of ' 1 ' since
last Violation
Polarity of
preceding
'1'
Odd Even
Negative 000 V
-
B
+
OOV
+

Positive 000 V + B
-
00 V
-

30 CHL PCM SYSTEM ITI/SHYAM
DC-DC CONVERTER . CONTROL CARD
10 NO OF SIGNALLING CARD . TP CARD
SIGNALLING MDX . VOICE OR DATA CARD (5 NO.)
47
4W DATA/SPEECH CARD
4W SPEECH
4W DATA CARD(64Kb/S)
Attenuator 0.5,1,2,4dB

48
PCM Transmission System
The advantages of PCM are:

Relatively inexpensive digital circuitry may be used
extensively.
PCM signals derived from all types of analog sources
may be merged with data signals and transmitted over
a common high-speed digital communication system.
In long-distance digital telephone systems requiring
repeaters, a clean PCM waveform can be regenerated
at the output of each repeater, where the input consists
of a noisy PCM waveform.
The noise performance of a digital system can be
superior to that of an analog system.
The probability of error for the system output can be
reduced even further by the use of appropriate coding
techniques.
DIGITAL MULTIPLEXING
European digital signal 1
PCM30 (Pulse Code Modulation, 30 voice channels)
G.703, G.704, G.732 (ITU recommendations)
PDH basic system (Plesiochronous Digital Hierarchy)
Features
Time multiplex
Bit rate 2.048 Mbit/s 50 PPM
32 channels with 64 kbit/s each
30 voice channels, 1 synchronization/message, 1 signalling
75 coax or 120 symmetrical twisted pair
Rectangular pulses, HDB3 line coding
PDH E1 signal
52
Europe bit rate(Mb/s)

2.048

8.448

34.368

139.264

565.148

Telephone
channel
30

120

480

1920

7680

SDH

2.5Gb/s

Telephone
channel

North America bit
rate(Mb/s)
24

1.544

48

3.152

96

6.321

672

44.736

4032

274.176

Bit rate for PCM & Higher Order Mux
European standard : A-Law
30 + 2 control channel = 32
Bit rate= 32 x 8 bit/sample x 8000 sample/s
= 2.048 Mb/s
North American standard (NAS) : -Law
For every 24 sample, 1 bit is added for
synchronization
For 24 sample => 24 x 8 bit/sample + 1 bit
= 193 bits
Bit rate= 193 x 8000 = 1.544 Mb/s
Needs Multiplexing Process of transmitting two or more
signals simultaneously
53
DIGITAL HIERARCHIES BASED ON THE 1544 KBIT/S PCM PRIMARY MULTIPLEX
EQUIPMENT (BELL LAB 1968)
Level in
hierarchy
Bit rate Trans. line
First level 1544 kbit/s T1
Second level 6312 kbit/s T2
Third level 46304 kbit/s L5 (Jumbo Grp)
Fourth level 280000 kbit/s WT4 (Wave guide)
Fifth level 568000 kbit/s T5
PLESIOCHRONOUS DIGITAL HIERARCHY
(PDH)
2/25/2014 55
PDH
(E5)
564.992
Mbit/s
E1
2.048 Mbit/s
DSMX
64k/2M
MStD
PCM

DIV
LE2
E2
8.448 Mbit/s
E2
2/8
E3
34.368 Mbit/s
E3
8/34
E4
139.264 Mbit/s
E4
34/140
Hierarchy
56
E5
140/565
Specification at Output Port
E1 E2 E3 E4 E5
Bit rate in Mbit/s
2.048 8.448 34.368 139.264 565.992
Clock tolerance
50
PPM
30
PPM
20
PPM
15
PPM
5 PPM
Frame length in
bits/Time in s
256bit
125s
848bit/
100.38
1536bit/
22.375
1928bit/
21.024
Stuffing rate per
frame
0.42 0.4357 0.4192
Impedance in
120 75 75 75 75
Line code
HDB
3
HDB3 HDB3/
CMI
CMI
SIGNAL :-
PLESIOCHRONOUS SIGNAL
SIGNALS WHOSE CLOCK CAN VARRY
INDEPENDENT OF ONE ANOTHER BUT THE
RANGE OF SIGNAL VARIATION IS RESTRICTED
WITHIN CERTAIN LIMITS.
Synchronous Signal
Asynchronous Signal
MULTIPLEXING OF SYNCHRONOUS DIGITAL
SIGNALS
Block interleaving :
Bunch of information taken at a time from each
tributary and fed to main multiplex output
stream. The memory required will be very
large.
Bit interleaving :
A bit of information taken at time from each
tributary and fed to main multiplex output
stream in cyclic order, a very small memory
is required.
Justification
In general, incoming tributaries have
independent clocks. In that case, it is
inevitable that clock rate of a tributary and the
(divided) clock rate of the multiplexer (in
second order TDM, it is 8448/4 = 2112 KHz)
are not the same. Without any precautions,
the result will be Slip.
The Frame Alignment Principle
Justification
Justification
MULTIPLEXING OF ASYNCHRONOUS
SIGNAL
Positive justification : Common synchronization bit
rate offered at each tributary is higher than the bit
rate of individual tributary.
Positive-negative justification : Common
synchronization bit rate offers is equal to the
nominal value.
Negative justification : Common synchronization
bit rate offered is less than the nominal value.
Incoming Bit Rate Too High
Incoming Bit Rate Too Low
E2: 8,448 Mbit/s 30 ppm
>
E1: 2,048 Mbit/s 50 ppm
E1: 2,048 Mbit/s 50 ppm
E1: 2,048 Mbit/s 50 ppm
E1: 2,048 Mbit/s 50 ppm
Multiplexing 4 E1 signals PDH E2 signal
67
t A
2 3 4 5 6 7 8 9 10
2 3 4 5 6 7 8 9 10 11 S
Suppressing reading clock
Insert stuffing bit
11 1
f
write

1
f
read

Positive justification PDH E2 signal
68
Block 1
200 info bits
Block 2
208 info bits
Block 3
208 info bits
Block 4
204-208 info bits
1..12
848 bit
100,38 s
13..212 5..212 5..212 9..212
U N
Alarms Frame alignment pattern
0 0 1 0 0 0 1 1 1 1
1 2 3 4 1 2 3 4 5 6 7 8 1 2 3 4
Justification control bits
1 bit per channel and frame
(transmitted 3 times)
0=no stuffing; 1=stuffing
Justification bits
1 bit per ch. and frame
no stuffing: information
stuffing: fixed value
Frame structure PDH E2 signal
69
8Mb FRAME STRUCTURE
Frame Alignment
Bunched words (first 10 bits in second order
multiplex frame) is preferred to distributed
bits to prevent imitation by any other bit
sequence.
The sequence used in Second and Third Order
MUX is 1111010000.


Four bit stream of 2048 Kb/s are multiplexed. The resulting bit
stream of 8448 Kb/s can be thought of being composed as
follows :- Per tributary=84484=2112Kb/s
No of frame per second =8448kb/s848=996210000

Nominal bit rate : 2048 Kb/s
Frame alignment information Per tributary: 30 Kb/s
Justification control digits : 30 Kb/s
Sub total : 2108 Kb/s
Justification digits : 2112-2108= 4 Kb/s used to
allow over speed
Justification rate per frame and E1 signal 0.42 bit

Block 1
372 info bits
Block 2
380 info bits
Block 3
380 info bits
Block 4
376-380 info bits
1..12
1536 bit
44,6927 s
13..384 5..384 5..384 9..384
U N
Alarms Frame alignment pattern
0 0 1 0 0 0 1 1 1 1
Frame structure PDH E3 signal
1 2 3 4 1 2 3 4 5 6 7 8 1 2 3 4
Justification control bits
1 bit per channel and frame
(transmitted 3 times)
0=no stuffing; 1=stuffing
Justification bits
1 bit per ch. and frame
no stuffing: information
stuffing: fixed value
72
PDH E3 signal
2nd multiplex level of PDH
Multiplexing of four E2 tributaries
Features
Bit rate 34,368 Mbit/s 20 ppm.
Frame duration 44,6927 s
Frame frequency 22,375 kHz
Bits per frame 1536
Bit interleaved multiplexing of 4 E2 signals
1 justification bit per frame and E2 signal
3 justification control bits per frame and E2 signal
Justification rate per frame and E2 signal 0,4357 bit
73
Block 1
472 info bits
Block 2, 3, 4, 5
je 484 info bits
Block 6
480 - 484 info bits
1..16
2928 bit
21,024 s
17..488 5..488 9..488
Alarms
D N
Frame alignment pattern
0 0 1 0 0 0 1 1 1 1 1 0
Y
1
Y
2
Data communication channel
1 2 3 4 1 2 3 4 5 6 7 8
Justification control bits
1 bit per channel and frame
(transmitted 5 times)
0=no stuffing; 1=stuffing
Justification bits
1 bit per ch. and frame
no stuffing: information
stuffing: fixed value
Frame structure PDH E4 signal
74
PDH E4 signal
3rd multiplex level of PDH
Multiplexing of four E3 tributaries
Features
Bit rate 139,264 Mbit/s 15 ppm
Frame duration 21,024 s
Frame frequency 47,564 kHz
Bits per frame 2928
Bit interleaved multiplexing of 4 E3 signals
1 justification bit per frame and E3 signal
3 justification control bits per frame and E3 signal
Justification rate per frame and E3 signal 0,41912 bit
75
Specification at Output Port (PCM)
Pair(s) in each direction One Coaxial
Pair
One Symmetrical
Pair
Test Load Impedance 75 ohm 120 ohm
(rest.)
Nominal peak voltage of a
mark
2.37 V 3 V
Peak voltage of a space 0+0.237 V 0+0.3 V
Nominal pulse width 244 ns 244ns
Ratio of amplitude of +ve and
ve pulses at the centre of
pulse interval
0.95 to
1.05
0.95 to 1.05
Ratio of widths of +ve and ve
pulses at the nominal half
amplitude
0.95 to
1.05
0.95 to 1.05
Specification at Output Port (8M)
Pair(s) in each direction One Coaxial Pair
Test Load Impedance 75 ohm (rest.)
Nominal peak voltage of a mark
(pulse)
2.37 V
Peak voltage of a space (no pulse) 0 + 0.237 V
Nominal pulse width 59 ns
Ratio of amplitude of +ve and ve
pulses at the centre of pulse
interval
0.95 to 1.05
Ratio of widths of +ve and ve
pulses at the nominal half
amplitude
0.95 to 1.05
Specification at Output Port (34MB)
Pair(s) in each direction One Coaxial Pair
Test Load Impedance 75 ohm (rest.)
Nominal peak voltage of a mark
(pulse)
1.0 V
Peak voltage of a space (no pulse) 0 + 0.1V
Nominal pulse width 14.55
Ratio of amplitude of +ve and ve
pulses at the center of pulse
interval
0.95 to 1.05
Ratio of widths of +ve and ve
pulses at the nominal half
amplitude
0.95 to 1.05
Specification at Output Port (140Mb)
Pair(s) in each direction One Coaxial Pair
Test Load Impedance 75 ohm (rest.)
pk. to pk. Voltage 1 + 0.1 V
Rise time between 10%
and 90% amplitude of
measured amplitude
< 2 ns
Return loss > 15 dB for 7 MHz to 210
MHz
DIGITAL TRANSMISSION ANALYSER
80
Performance Criteria
Digital Transmission Analyser (DTA) is used for
the measurement of both BER and Jitter.
Digital Transmission - Performance Criteria (
General)
1 in 10
6
(1.OE 6) : Better
1 in 10
5
(1.OE 5) : Good
1 in 10
4
(1.OE 4) : Reasonably good
1 in 10
3
(1.OE 3) : Just Acceptable
More than 1 in 10
3
: Unacceptable
Bit errors greatly affect data service.
For data channels 1 in 10
9
(1.OE 9) is normally realizable.

81
Quality Parameters
The quality parameters are:
Error Seconds (ES)
Severely Error Seconds (SES)
Non Severely Error Seconds (NSES)
Degraded Minutes (DM).

82
Quality Parameters
Error Seconds (ES): Number of one-second
intervals with one or more errors.
Severely Error Seconds (SES): Number of one-
second intervals with an error rate, worse
than 1.OE-3
Non-Severely Error Seconds (NSES): Number
of one-second intervals with an error rate,
better than or equal to 1.OE-3.

83
Degraded Minutes (DM): Number of one-second
intervals with a bit error rates worse than 1.OE-6.
Available and non-available time
A period of available time begins with a period of
ten consecutive seconds each of which has a BER
better than 1.0E-3. These 10 seconds are
considered to be available time.
A period of unavailable time begins when the bit
error rate in each second is worse than 1.0E-3 for
a period of 10 consecutive seconds. These 10
consecutive seconds are considered to be
unavailable time.

84
JITTER
Jitter is the undesired deviation from true
periodicity of an assumed periodic signal in
electronics and telecommunications, often in
relation to a reference clock source. Jitter may
be observed in characteristics such as the
frequency of successive pulses, the signal
amplitude, or phase of periodic signals. Jitter
is a significant, and usually undesired, factor in
the design of almost all communications links.
85
JITTER ASPECT OF MULTIPLEX
EQUIPMENT
Jitter introduced by the multiplex system:
1. Jitter introduced due to the routine insertion of the
frame alignment words and of the service digits
and justification instructions.
2. Justification jitter.
3. Waiting time jitter :-waiting time jitter which is due
to phase difference between write and read clock
and varies from frame to frame, has a low
frequency component and cannot be jittered out
by P.L.L. at the demultiplexer
skgochhayat@gmail.com 87