A Scalable High Performance Virus-Detection Processor Against a Large Pattern Set for Embedded Network Security

Presented by

M.Siva Ram Prasad

12MQ1D5706 VLSI & SD

Under The Guidance of Mr. D.Sridhar M.Tech, Assistant Professor in SVIET.

CONTENTS
Introduction Aim Abstract Algorithm Block Diagram Tools Comparison Advantages Applications Conclusion References

AIM
Network security has always been an important issue and its

application is ready to perform powerful pattern matching to

protect against virus attacks, spam and Trojan horses. The goal is to provide a systematic virus detection hardware solution for network security for embedded systems. Instead of placing entire matching patterns on a chip, our solution is based on an antivirus processor that works as much of the filtering information as possible onto a chip

ABSTRACT
In this project proposed to achieve a high-throughput, low-

power, and low-cost virus-detection processor for mobile

devices. The proposed virus detection processor is realized with the dual-port AND-type match-line scheme which is composed of dual-port dynamic AND gates. The dual-port designs reduce power consumption and increase storage

efficiency due to shared storage spaces.

VIRUS
A virus is a computer program that can copy itself and infect a computer. The term "virus" is also commonly but erroneously used to refer to other types of malware, including but not limited to adware and spyware programs that do not have the reproductive ability. A true virus can spread from one computer to another (in some form of executable code)

VIRUS DETECTION PROCESSOR SHOULD HAVE

1) The system throughput should reach up to 1 Gbps for supporting real-time

virus detection in mobile devices adopting 4G wireless systems.

2) The scalability of handling more than ten thousands patterns is required for

versatile network protection. In addition, the system must be highly flexible

to accommodate the rapidly increasing new virus patterns.

3) Power consumption is the most important design consideration for mobile

devices.

EXISTING SYSTEM
Aho and Corasicks algorithm (AC), which introduces a linear-time algorithm for multi-pattern search with a large finitestatema-chine.

In contrast, heuristic approaches are based on the Boyer- Moore algorithm, which was introduced in 1977. Its key feature is the shift value,which shifts the algorithms search window formultiple characters when it encounters a mismatch.

USED ALGORITHM
BLOOM ALGORITHM

SHIFT -SIGN SIGNATURE ALOGRITHAM

Wu-Manber algorithms and have even developed for specialized circuits to increase the scanning speed

BLOCK DIAGRAM

Tools
Xilinx ISE 14.3 VHDL

COMPARISON TABLE
Quantity Existing work
126.861MHz 5.310ns 14752 29504 29504 227028KB 376

Proposed work
534.334MHz 5.310ns 777 770 1216 227264KB 263

Maximum Frequency Minimum period Number of slice registers Number used as Flip Flops Number of 4 input LUTs Peak memory usage Number of bonded IOBs

ADVANTAGES
high-throughput low-power low-cost

DIS-ADVANTAGES
. In this project we are dealing with three states(1 0 and X).

. Dealing with that dont care is advantage, but to

define that dontcare is somehow difficult.

APPLICATIONS
In wireless devices like Bluetooth, Infrared rays communication.

Our project can be applied to personnel computers also.

CONCLUSION
Many previous designs have claimed to provide high performance, but the memory gap created by using external memory decreases performance because of the increasing size of virus databases.

Furthermore, limited resources restrict the practicality of these algorithms for embedded network security systems. Two-phase heuristic algorithms are a solution with a tradeoff between performance and cost due to an efficient filter table existing in internal memory; however, their performance is easily threatened by malicious attacks.

REFERENCES

K. J. Lin and C. W. Wu, A low-power CAM design for LZ data compression,IEEE Trans. Comput., vol. 49, no. 10, pp. 11391145, 2000. T. Ikenaga and T. Ogura, A fully parallel 1-MbCAMLSI for real-time pixel-parallel image processing, IEEE J.Solid-State Circuits, vol. 35, no. 4, pp. 536544, 2000 N. F. Huang, W. E. Chen, J. Y. Luo, and J. M. Chen, Design of multifield IPv6 packet classifiers using ternary CAMs, in Proc. IEEE Int. Conf. Global Telecommunications, 2001, vol. 3, pp. 18771881. Y. H. Cho and W. H. Mangione-Smith, A pattern matching coprocessor for network security, in Proc. IEEE 2005 Int. Conf. Design Automation,pp. 234239. L. Tan and T. Sherwood, A high throughput string matching architecture for intrusion detection and prevention, in Proc. IEEE Int. Symp. Computer Architecture, 2005, pp. 112 122.

M. Yadav, A. Venkatachaliah, and P. D. Franzon, Hardware architecture of a parallel pattern matching engine, in Proc. IEEE Int. Symp. Circuits and Systems, 2007, pp. 13691372.

THANK YOU