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McBSP

De Luis Olivera Alfredo Espinosa Hector

McBSP

El McBSP esta basado en las interfaces estndar del puerto serial encontrado en las plataformas TMS320C2000 y C5000. Este puerto almacena muestras seriales en un buffer de memoria automticamente, con o sin la ayuda del controlador EDMA. El DSP6713 tiene dos puerto serial multicanal con buffer (McBSP0 y McBSP1). El McBSP0 es el que controla de manera unidireccional y es configurado a travs de cinco registros que controlan el flujo a travs del McBSP1. El McBSP1 es usado como un canal de comunicacin bidireccional de datos y proporciona :

McBSP

Comunicacin Full - Duplex.

Registros de datos de doble buffer para flujo continuo de datos.


Tramado independientes para recepcin y transmisin. Interface directa a codecs estndar, chips de interface analgico (AICs) y otros dispositivos A/D y D/A conectados serialmente.

Capacidades

Transmisin y recepcin multicanal de 128 canales. Selector para determinar el tamao del dato (8,12,16,20,24 y 32 bits). Transferencia inicial de 8 bits con LSB o MSB. Polaridad programable para tramas sincronizadas. Reloj interno altamente programable y generador de tramas.

Registros del McBSP para el DSP C621x/C671x

Data Receive Register (DRR)

El DRR contiene el valor que va a ser escrito al bus de datos.

Data Transmit Register (DXR)

Serial Port Control Register (SPCR)

Receive Control Register (RCR)

The receive control register (RCR) configures parameters of the receive operations.

Transmit Control Register (XCR)

The transmit control register (XCR) configures parameters of the transmit operations.

Sample Rate Generator Register (SRGR)

The sample rate generator register (SRGR) controls the operation of various features of the sample rate generator.

Multichannel Control Register (MCR)

The multichannel control register (MCR) contains fields that control the multichannel selection mode. The enhanced 128-channel selection mode (selected by the RMCME and XMCME bits), which allows the McBSP to select 128 channels at any time, is only available on the C64x DSP.

Receive Channel Enable Register (RCER)

The receive channel enable register (RCER) is used to enable any of the 32 elements for a receive. Of the 32 elements, 16 belong to a subframe in partition A and the other 16 belong to a subframe in partition B. The RCEA and RCEB fields in RCER enable elements within the 16-channel elements in partitions A and B, respectively. The RPABLK and RPBBLK bits in MCR determine which 16-element subframes are selected.

Transmit Channel Enable Registers (XCER)

The transmit channel enable register (XCER) is used to enable any of the 32 elements for a transmit. Of the 32 elements, 16 belong to a subframe in partition A and the other 16 belong to a subframe in partition B. The XCEA and XCEB fields in XCER enable elements within the 16-channel elements in partitions A and B, respectively. The XPABLK and XPBBLK bits in MCR determine which 16-element subframes are selected.

Pin Control Register (PCR)

The serial port is configured via the serial port control register (SPCR) and the pin control register (PCR). The PCR is also used to configure the serial port pins as general-purpose inputs or outputs during receiver and/or transmitter reset. The PCR contains McBSP status control bits.