MIMD Systems

Each PE Works independently of others.

Processor 1 is said to be independent of processors 2,3..N at any instant, if and only if task being executed by processor 1 has no interactions with tasks executed by processor 2,3.N and vice-versa.

However results from processor X may be needed by processor Y.

So processors must have the capability to communicate the results of the tasks it performs to other tasks requiring them.

This can be done by directly sending the results to requiring processors or storing them in a shared memory.

Which causes the basis of 2 popular MIMD organization (a) Shared Memory or Tightly Coupled Architecture. (b) Message Passing or Loosely Coupled Architecture.

Shared Memory Architecture/Tightly Coupled Architecture

The results of the computatio n are stored in the memory by the processor that executed the task.
Each processor is a full fledged SISD, capable of fetching instructions from the memory and executing them on the data retrieved from the memory. No processor has local memory of its own.

Any Processor i can access any memory module j through interconnec tion network.

If the results are required by other tasks, they may be accessed from the memory.

Called Tightly Coupled Architecture, since the processors are interconnected such that the interchange of data between them through the shared memory is quite rapid.

Memory access time is same for all processors hence also called as Uniform Memory Architecture (UMA).

If Processors are different 32-bit and 16-bit and memory consists of 32-bit words, each memory word must be converted into words for the use of 16-bit processors. This is an Overhead.

Another problem is Memory Contention which occurs when two or more processors try to access same shared memory block.

Since memory block can be accessed only by one processor at a time, all the others requesting the same block must wait until first processor is through using it.

If two processors simultaneously request the access to the same memory block, one of the processors is given preference over others.

Message Passing Architecture/Loosely Coupled Architecture

There is no shared memory at all in the system, each processor has a local memory block attached to it.
If data exchange is required between two processors in this configuration, the requesting processor i sends a message to j in whose memory the requested data is stored.
In reply to this request the processor j ASAP reads the requested data from its memory and passes it on to processor i through interconnecti on network

The conglomeration of all local memories is the total memory that the system possesses. It is also called Distributed MIMD.

The requested processor finishes its task under process then access its memory for the requested data and passes it on to interconnection network which routes it towards the requesting processor.

For all this time requesting processor sits idle incurring large overheads.

Memory access time varies between the processors and hence these architectures are known as NonUniform Memory Access (NUMA).

Since it works on message passing, only one processor accesses to memory block hence there is less memory contention problem.

Comparison Of Tightly Coupled Vs. Loosely Coupled Architecture

Tightly Coupled Architecture 1. More rapid data interchange between processors in comparison to Loosely Coupled Architecture. 2. More memory contention problem. Loosely Coupled Architecture 1. Less rapid data interchange between processors in comparison to Tightly Coupled Architecture. 2. Less memory contention in comparison to tightly coupled architecture. 3. Also called as message passing architectures, NUMA, Multicomputer system.

3. Also called as shared memory architectures, UMA, Multiprocessor system.

Examples of Tightly Coupled Multiprocessors:

1. Cyber-170 Architecture

Consists of two subsystems

(a) Central processing subsystem

(b) Peripheral processing subsystem

Both have access to common central memory

Through CM Controller, which is a high speed Cross bar switch

Also have secondary memory(opti onal) called as Extended Core Memory(ECM)

1. A Cyber-170 Multiprocessor Configuration with two processors

CM and ECM form two level memory hierarchy.

CMC becomes switching centre and performs function of ISIN, IOPIN and PMIN.

2. Honeywell 60/66 Architecture

Every central processor and every I/O Mux is connected to every system controller (SC).

This provides adequate redundancy in paths for high availability.

In event of failure on the SC, all IOMs are still accessible by each processor.

SC acts as a memory controller for its associated pair of memory modules.

A Honeywell 60/66 multiprocessor system

SC also acts as an intelligent switch to route interrupts and other communications among the various system components. When more than one element attempts to access the same memory module, the corresponding SC resolves the conflict. This triple redundancy enhances availability and fault tolerance.

3. The PDP-10 multiprocessor

There are two configurations of PDP-10 multiprocessor system with multi-ported memory modules. Each CPU has a cache of 2K words, where each word is 36 bits. Fig. shows Asymmetric MasterSlave configuration, the two processors are identical, but asymmetry is result of connection of peripherals to the master only. Slave can not initiate peripheral operations nor respond to an interrupt directly.

 Fig. shows a symmetric configuration, both processors are connected to a set of shared fast and slow peripherals, however each data channel is attached to one processor, which is the only processor that can use it.

Slow peripherals are connected to both processors via a switch.

There is no cache invalidate interface between them. It is assumed that a software solution is used to enforce cache consistency. Inherent redundancy in a multiprocessor system probably increases its ability to be fault tolerant.