Nanotechnology: Spatial

Computing Using Molecular

Electronics

Mihai Budiu
joint work with
Seth Copen Goldstein
Dan Rosewater
 Intersection of Three Areas
Nanotechnology Reconfigurable
computing

Computer
architecture
SSS April 20, 2001 2
 Prophecies, A Risky Endeavor
There is no reason anyone would want a computer in their home.
--- Ken Olson

I think there is a world

market for maybe five There is not the slightest
computers. indication that nuclear
--- T. J. Watson energy will ever be
obtainable.
--- Albert Einstein

640K ought to be enough for everybody.

--- Bill Gates

I will propose this semester.

--- Anonymous
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 Moore’s Law

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 Moore’s Second Law

X 1000$
generation

Plant cost Mask cost

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 Our Proposal
Nanotechnology Reconfigurable
+ cheap Computing
+ high-density _ + defect tolerant
+ low-power + high performance
– unreliable – low density
_ ++++
_ + +
_

Computer architecture
+ vast body of knowledge
– expensive
– high-power
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 Paradigm Shift

Executable Configuration

Complex fixed chip Dense, regular structure

+ +
Program Configuration
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 Outline
 Introduction
• Reconfigurable computing
• Nanotechnology
• Nano-architecture proposal
• Preliminary results
• Conclusions and Future Work

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 Reconfigurable Computing
• Back to ENIAC-style computing

• Synthesize one machine to solve one

problem
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 Island-Style RC Architecture
Interconnection
network

Universal gates
and/or
storage elements

Programmable Switches

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Main RC Ingredient: RAM Cell
0
a0 0 data a0
0 a1 a1 & a2
a1
1

Universal gate = RAM

data in
0
control

Switch controlled by a 1-bit RAM cell

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 Place and Route

int reverse(int x)
{
int k,r=0;
for (k=0; k<64; k++)
r |= x&1;
x = x >> 1;
r = r << 1;
}
}
int func(int* a,int *b)
{
int j,sum=0;
for (j=0; *a>0; j++)
sum+=reverse(*b

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Kernel Speedup Using PipeRench
Times Over 300Mhz UltraSparc-II

1000

189.7

100 63.3 57.1

42.4
26.0 29.0
15.5
11.3 12.0
10

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 Defect Tolerance

Despite having >70% of the

chips defective, Teramac works
flawlessly.

Compilation has two phases:

• defect detection through
self-testing
• placement for
defect-avoidance

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 Outline
 Introduction
 Reconfigurable computing
• Nanotechnology
• Nano-architecture proposal
• Preliminary results
• Conclusions and Future work

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 Nanotechnology

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 Predicted Features
• Low Power: 1010 gates use less than 2 W
(compare to 3x107 transistors using 100 W in
CMOS)
• Low cost
(nanocents/gate)
• Small size
(105 factor area gain)

Nano-RAM cell
.
In yellow: a CMOS RAM cell
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 Nano-wires
• carbon nanotubues, Si, metal
• >2nm diameter, up to mm length
• excellent electrical properties

A carbon nanotube: one molecule

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 Nano-switch

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 Nano-switch Between
Nano-wires

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 Self-assembly

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 No Complex Irregular
Structures

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 No Three-Terminal Devices

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 Diode-resistor Logic

V AND

A B VDD

B Input 1 Output
A *^ B Input 2

A*B

Nano-implementation Electrical equivalent

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 Nanoscale Latches

Provide:
• signal restoration (amplification)
• clocking (synchronization)
• memory
data out

D
clock

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 High Defect Rate

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 Outline
 Introduction
 Reconfigurable computing
 Nanotechnology
• Nano-architecture proposal
• Preliminary results
• Conclusions and future work

SSS April 20, 2001 27

The nanoBlock (3-in to 3-out Logic)
CMOS
Inputs
+Vdd

clk
Gnd

Gnd
clk
Outputs

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 Interconnecting nanoBlocks
Switch block

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 Global View

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 Many Clusters = nanoFabric
cluster

long-lines
Control

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 Compilation
int reverse(int x)
{
int k,r=0;
for (k=0; k<64; k++)

1. Program r |= x&1;
x = x >> 1;
r = r << 1;
}
}

Computations
3. Split-phase Abstract & local storage
Machines
Unknown latency ops.

5. Configurations placed
independently

7. Placement on chip

SSS April 20, 2001 32

 Outline
 Introduction
 Reconfigurable Hardware
 Nanotechnology
 Nano-architecture proposal
• Preliminary results
• Conclusions and Future work

SSS April 20, 2001 33

 A Limit Study of Performance
A graph of the whole program execution:

Basic block Control-flow transfer

Memory write

Memory read Memory word

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 units

50000

0
100000
150000
200000
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SSS April 20, 2001

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35
Typical Program Graph (g721_e)
Memory reads
Control flow transfer

100% code cluster

100% memory cluster

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Typical Program Graph (g721_e)
Memory reads
Control flow transfer

code

memcpy
memory
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Program Graph After Inlining memcpy

memcpy

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 times slower than native

0
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SSS April 20, 2001

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Application Slowdown

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39
 How Time Is Spent
No caches: reads expensive
100%
90%
80%
70%
60% idle
percent

50% execution
40% control flow
30% register traffic
20%
10%
0%
No speculation
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SSS April 20, 2001 40

 Future Work
• Better nano-devices

• More accurate hardware models in

simulations

• Compilation technology
SSS April 20, 2001 41
 Conclusions
• Electronic nanotechnology promises to
transcend the limitations of CMOS
• Nanofabrics are very well suited to
reconfigurable computation
• 109-gate designs can be managed through
hierarchies of abstract machines

SSS April 20, 2001 42