Modelsim de

ModelSim DE
CADware s.r.o. Prezentuje ve spoluprci s firmou
ModelSim DE
Leading Single & Mixed Language Simulation
Native single kernel verification environment

Verilog 1995, 2001, 2005 VHDL 1987/1993/2002/2008 !stemVerilog for "esign !stemVerilog an" # L assertions !stem$ %it& $V an" 'L(, $, $)) *o+tion,
-roa"est t!+e s.++ort at lang.age /o.n"aries

$om+onent/mo".le instantiation ignal +!0 $ control, o/serve an" connect met&o"s 1nl! sim.lator a/le to s&are t!+e "efinitions %ritten in one +ackage in /ot& VHDL an" !stemVerilog
#reserving f.ll /enefits of strong t!+e c&ecking
Mentor Graphics ModelSim DE .!
ModelSim DE
Leading Single & Mixed Language Simulation
2ntegrate" "e/.g an" anal!sis ca+a/ilities

$om+re&ensive root ca.se anal!sis $overage anal!sis an" re+orting $omman"s/342 consistent across lang.ages, H5 +latforms an" a/straction levels
ec.re2# s.++ort

Hig&er +erformance 6ilin7 2# Native s.++ort for VHDL an" Verilog
Lin.7 an" 5in"o%s s.++ort

ModelSim DE
Leading Assertion and Coverage technology
V8 an" # L assertions

2m+rove" verification effectiveness 2m+rove" time to "e/.g

2"entif! fail.res as t&e! occ.r (o"el im D9 a"vance" assertion "e/.gging
8ssertion /ro%sing
1VL assertion li/rar! rea"! $o"e $overage

9fficient coverage collection

4nifie" $overage Data/ase *4$D-, :anking an" (erging
2m+rove verification test +ro".ctivit!
Agenda
8ssertions De/.g ; 8nal!sis $overage
Assertion Based Verification Improves Time-To-Bug

Design Under Test
Reference Model
&

Lurking bugs: found late in the design cycle
&
8-V "etects /.gs at t&e so.rce, saving val.a/le "e/.g time 8-V "etects /.gs misse" /! to+<level test /enc&es
W at is an Assertion!
8 concise "escri+tion of =.n>"esire" /e&avior
+ re# ac%
Example intended behavior
'
"After t e re#uest signal is asserted$ t e ac%no&ledge signal must come ' to ( c)cles later*
W o Uses Assertions!
1mm22 1mm22I Iassume assumet t ee 3S 3Sinputs inputsare are mutuall) e4clusive mutuall) e4clusive 5unctional 5unctionalspec specsa)s sa)s A36 &ill follo& RE7 A36 &ill follo& RE7 &it &it in in8-', 8-',cloc% cloc% c)cles c)cles Spec2 Spec2sa)s sa)st t at atRE7 RE7 must not drop /efore must not drop /efore A36 A36is isreceived2 received2
Must Mustremem/er0 remem/er0 TT is is a is is a''- ot otstate state mac ine mac ine Better Better&arn &arnot ot ers ers a/out t ose a/out t ose cc ec%sum ec%sumgotc gotc as as
W W at atI Ireall) reall)need needto to %no& is o& man) times %no& is o& man) times aatransfer transferD9ES:;T D9ES:;T complete complete
3oncise and E4pressive

SVA Assertion
property req_ack; SystemVerilog @(posedge clk) $rose(req) |-> ##[1:3] $rose(ack); endproperty as_req_ack: assert property(req_ack); al ays @(posedge req) Verilog !eg"n repeat (1) @(posedge clk); #ork: pos_pos !eg"n @(posedge ack) $d"splay($%ssert"on &'ccess$($t")e); d"sa!le pos_pos; end !eg"n repeat (*) @(posedge clk); $d"splay($%ssert"on +a"l're$($t")e); d"sa!le pos_pos; end ,o"n end -- al ays
'
re# ac%
Example intended behavior
1D< Assertion
ABV Improves Time-To-3overage

Design Under Test
Reference Model
8-V reveals internal str.ct.ral coverage 8-V +ro".ces actiona/le metrics to im+rove coverage
Best Time To Bug Resolution
8ssertions i"entif! fail.re closest to "esign fail.re

Need ability to visualize the assertion Need ability for root cause analysis
(o"el im D9 &as t&e /est vis.ali?ation an" "e/.g tools

Lang.age ne.tral "e/.g s.ite 8ssertion 8nal!sis

Lists all assertions at current hierarchy S/W logic analyzer View assertion and its signals Clear indication of assertion status: active/inactive/ ass/fail !eco" oses assertion for best understanding Source code and gra hical dataflow
5aveform Vie%ing
8ssertion animation

$om+lete .ser interface tools for root ca.se anal!sis
Vie&ing Assertions in t e Wave

=reen mid-line indicates assertion is active =reen triangle indicates assertion passed Red inverted triangle indicates assertion failure
Blue lo&-line indicates assertion is inactive Simpl) D>D Assertions from Assertion Bro&ser into Wave Windo& to vie& assertions Assertions can /e e4panded to vie& all signals associated &it t e assertion
Vie& Multiple Assertion T reads

Blue /o4 a/ove t read indicates start of ne& t read RM3 on start of t read /o4 invo%es ATV
Automatic T read count integer E4pand to see individual t read

5ailure Resolution Assertion T read Vie&er
:oot ca.se anal!sis

o.rce co"e 5ave %in"o% Vis.ali?e in assertion t&rea" %in"o%

Strategies for Adopting ABV
+ecif! "esign intent
5&at 2 t&o.g&t 2 "esigne"

2"entif! &ig&<level elements in !o.r /locks@
A2A1s, 8r/iters, (emories, A (s
Declarations Be! 1+erations

#.t arit&metic overflo% on arit&metic o+s 3.ar" all mo".le 2/1
$orner cases

(ake s.re test e7ercises "iffic.lt scenarios (ake s.re illegal sit.ations are &an"le" correctl!
+ecif! environment ass.m+tions

5&at ot&er /locks are "oing 2n+.t ass.m+tions 5&at t&e test/enc& should /e "oing 8voi" "e/.gging false<negative test/enc& +ro/lems
Agenda
De/ug All <anguages And Anal)?e 3overage
$onsistent look an" feel for all lang.ages :oot ca.se isolation $overage anal!sis an" re+orting
3ommon control > /e avior for all &indo&s
An) &indo& can form a ta/ group &it an) ot er &indo&

En anced Wave Windo&
A.ll ca+a/ilities
HDL, !stem$, 'L( an" 8ssertion De/.g
$ross linke" %it& entire "e/.g environment 5aveform $om+are
2"entif! first fail.re
Logical Vie%s
Virt.al 1/Cects
ignals, A.nctions an" regions
5aveform management
Dataset sna+s&ot, s./set, clear, save, stats

Wave Windo& Delta Vie&ing

Tool/ar to control delta vie&ing
Same information in list form
Wave &indo& e4panded to s o& delta c anges
User Defined Radi4

"pus * signals &it > &it out radi4 :e& radi4 appears in pic% list Tcl command defines radi4
radi4 define States @ ''A/+++++++++++ B:9CUS1B$ ''A/++++++++++' BCUS1'B$ ''A/+++++++++'+ BCUS1,B$ 0 ''A/'++++++++++ BCUS1''B$ -default e4D
$reate m.lti+le +anes an" "rag an" "ro+ signals from one +ane to t&e ot&erD #o%erf.l 9"it an" earc& $a+a/ilities .n"er t&e 9"it (en.D $.rsors < m.lti+le, C.m+ to e"ge an" meas.rementD -ookmarks for marking m.lti+le %aveform vie%sD -alloon +o+.+ to "is+la! val.es
Wave Windo&
Wave Windo& Analog Displa)
2m+rove" analog %ave "is+la!
a"" %ave <min an" Ema7
97am+le of signal %it& val.es /et%een 0 an" 5

a"" %ave Eanalog Emin 0 Ema7 5 E&eig&t 100 Fm!GsignalH
$lam+ "is+la! to min/ma7 val.es
a"" %ave Eclam+analog I0J1K
ave %it& %rite format %ave FfileD"oH
Source Annotation
Annotation can /e lin%ed to active cursor Signal transitions
Stead) state values
1over over signal to get full pat > value
Te4tual Dataflo&E Tracing Signals
5ind reader of str/Fr
Select Signal t en RMB
Te4tual Dataflo&E Tracing Signals
5ind driverGsH of prd)Fr
Select Signal t en RMB
=rap ical Dataflo&E Tracing Signals Ain" $a.se of 4nkno%n %it& $&ase6
4sers can also "irect "ataflo% %in"o% to com+.te an" "ra% +at&s /et%een one +oint an" anot&er
Easing 3ausalit) Tracing Source 3ode 1)perlin%ing

9na/le so.rce co"e &!+erlinking
H!+erlinke" varia/les
#*
Easing 3ausalit) Tracing Source 3ode 1)perlin%ing
L.m+ to so.rce %in"o% an" &ig&lig&t varia/le "eclaration L.m+ t&ro.g& &ierarc&!
E4panded Data re#uires Data Management Message Vie&er

1rgani?e all sim.lation messages ort /! severit! or t!+e $ross links to ot&er %in"o%s for M.ick isolation of +ro/lems
Agenda
3ode 3overage
(eas.res lang.age coverage
Have !o. e7ec.te" eac&@

tatement -ranc& $on"ition 97+ression 1r 'oggle" eac& /it
-est .se" at /lock level

9asier to e7ercise co"e as+ects 9ns.res /locks are teste" ; rea"! for integration Lo% over&ea" 9as! to .se Hig& ca+acit! an" +erformance 4$D:ank 4$D- test files an" eliminate regression tests t&at "o not contri/.te to coverage metrics $om+re&ensive coverage e7cl.sion s.++ort
-.ilt<in

2m+rove verification t&ro.g&+.t
Unified 3overage DataBase GU3DBH

-est ca+acit! an" +erformance (ost com+re&ensive -ase tec&nolog! for N.esta Verification (anagement
ModelSim
Test 5unctional Assertion 3ode Engine 3overage 3overage +-in 5ormal User 3overage Test Specific Clan
Verification 3overage Anal)sis > Reporting
U3DB
(rd Cart)$ 9t er Mentor Tools > User Data
Data/ase Toolset$ load$ cop)$ merge$ ran%$ report$ anal)?e
Ran%ing 3overage Results

Cer Instance or DU
Include Time /ased goals
(erge an" anal!?e regression s.ite res.lts 2"entif! &ig&est !iel" coverage regression tests
9liminate non<contri/.ting tests

1TM< 3overage Vie&ing
Specif) design 1ierarc )
5or details clic% on specific Item
3ode 3overage Reporting Efficiencies

2ncl."es com+lete coverage res.lt "etails 9as! re+orting to management
3overage Totals
U3DBISimulation Details
ModelSim DE J2. 5unctional Verification
'&e /est e7ec.tion
2ntegrate" +latform availa/le to"a! 2m+rove verification effectiveness %it& assertions (ake ever! verification c!cle co.ntO
'&e /est tec&nolog!
'&e rig&t strateg!
Additional Mentor Croducts
Crocessor-driven Verification
8llo%s test efforts to s+an m.lti+le stages of t&e "esign < test re.se across t&e +roCect
Test/enc -/ased tests CrocessorDriven 3 test

1ig -<evel Simulation RT<I=ate Emulation Simulation Crotot)pe or 5C=As Cost5a/rication
N.esta $o"elink +rovi"es t&e critical feat.res to s.++ort +rocessor<"riven, incl."ing m.lti<core verification
1ard&areISoft&are 3orrelation
Multi-3ore Crocessor De/ug Environment
Mentor;s +-InK 5ormal Verification Solution Delivers 0

Hig&est ca+acit! an" +erformance 97tensive Design t!le .++ort mart integration of formal verification %it& sim.lation '&e largest li/rar! of assertion 2# in t&e in".str! 2nt.itive gra+&ical anal!sis an" "e/.g N.esta $overage "ata/ase ena/le"
T e Lproven; formal verification solution

+-InK 3D3 Verificaton
tr.ct.ral $D$ verification
8.tomaticall! i"entifies all clocks an" clock<"omain crossings *$D$s, 8.tomaticall! +roves $D$ #rotocols im.late $D$ +rotocol assertions (imics t&e metasta/ilit! effects in s!nc&roni?ers #rovi"es a meas.re of com+leteness for t&e test/enc& as relate" to metasta/ilit! iss.es
Verification of $D$ +rotocols

ilicon<acc.rate :'L sim.lation
8cc.rate $overage metrics
+-InK 3D3 M T e Benc mar% in 3D3 verification


Modelsim de

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Modelsim de

Caricato da

Copyright:

Formati disponibili

ModelSim DE

CADware s.r.o. Prezentuje ve spoluprci s firmou

Native single kernel verification environment

-roa"est t!+e s.++ort at lang.age /o.n"aries

#reserving f.ll /enefits of strong t!+e c&ecking

Mentor Graphics ModelSim DE .!

2ntegrate" "e/.g an" anal!sis ca+a/ilities

Hig&er +erformance 6ilin7 2# Native s.++ort for VHDL an" Verilog

Lin.7 an" 5in"o%s s.++ort

2m+rove" verification effectiveness 2m+rove" time to "e/.g

2"entif! fail.res as t&e! occ.r (o"el im D9 a"vance" assertion "e/.gging

1VL assertion li/rar! rea"! $o"e $overage

9fficient coverage collection

4nifie" $overage Data/ase *4$D-, :anking an" (erging

2m+rove verification test +ro".ctivit!

Mentor Graphics ModelSim DE .!

8ssertions De/.g ; 8nal!sis $overage

Mentor Graphics ModelSim DE .!

Assertion Based Verification Improves Time-To-Bug

Lurking bugs: found late in the design cycle

Mentor Graphics ModelSim DE .!

Mentor Graphics ModelSim DE .!

3oncise and E4pressive

Mentor Graphics ModelSim DE .!

ABV Improves Time-To-3overage

Best Time To Bug Resolution

8ssertions i"entif! fail.re closest to "esign fail.re

(o"el im D9 &as t&e /est vis.ali?ation an" "e/.g tools

Lang.age ne.tral "e/.g s.ite 8ssertion 8nal!sis

$om+lete .ser interface tools for root ca.se anal!sis

Mentor Graphics ModelSim DE .!

Vie&ing Assertions in t e Wave

Mentor Graphics ModelSim DE .!

Vie& Multiple Assertion T reads

Automatic T read count integer E4pand to see individual t read

5ailure Resolution Assertion T read Vie&er

:oot ca.se anal!sis

o.rce co"e 5ave %in"o% Vis.ali?e in assertion t&rea" %in"o%

Strategies for Adopting ABV

+ecif! "esign intent

5&at 2 t&o.g&t 2 "esigne"

2"entif! &ig&<level elements in !o.r /locks@

A2A1s, 8r/iters, (emories, A (s

Declarations Be! 1+erations

#.t arit&metic overflo% on arit&metic o+s 3.ar" all mo".le 2/1

+ecif! environment ass.m+tions

8ssertions De/.g ; 8nal!sis $overage

Mentor Graphics ModelSim DE .!

De/ug All <anguages And Anal)?e 3overage

3ommon control > /e avior for all &indo&s

An) &indo& can form a ta/ group &it an) ot er &indo&

En anced Wave Windo&

HDL, !stem$, 'L( an" 8ssertion De/.g

$ross linke" %it& entire "e/.g environment 5aveform $om+are

2"entif! first fail.re

ignals, A.nctions an" regions

Dataset sna+s&ot, s./set, clear, save, stats

Wave Windo& Delta Vie&ing

Same information in list form

Wave &indo& e4panded to s o& delta c anges

Mentor Graphics ModelSim DE .!

User Defined Radi4

Mentor Graphics ModelSim DE .!