Slides 11

Design Methodologies
Digital Integrated Circuits
Prentice Hall 1995
The Design Problem
Source: sematech97 A growing gap between design complexity and design productivity
Digital Integrated Circuits Design Methodologies Prentice Hall 1995
Design Methodology
Design process traverses iteratively between three abstractions: behavior, structure, and geometry More and more automation for each of these steps
Design Analysis and Verification

Accounts for largest fraction of design time More efficient when done at higher levels of abstraction - selection of correct analysis level can account for multiple orders of magnitude in verification time Two major approaches: Simulation Verification
Design Methodologies Prentice Hall 1995
Digital Data treated as Analog Signal

VD D Sp
Vin 5.0
Bp
Vou t
Gn ,p In Dn,p Out
Vo ut (V)
3.0 tpHL
1.0
Bn
Sn
1.0 0 0.5 1 t (nsec) 1.5 2
Circuit Simulation
Both Time and Data treated as Analog Quantities Also complicated by presence of non-linear elements (relaxed in timing simulation)
Representing Data as Discrete Entity

V VM 0 1 0
VDD Rp
t1
t2
CL
Discretizing the data using switching threshold
Rn
The linear switch model of the inverter

Circuit versus Switch-Level Simulation

5.0 CIN OUT[2]
Circuit
3.0 OUT[3] 1.0 1.0 0 5 10 15 time (nsec) 20
Switch
Prentice Hall 1995
Structural Description of Accumulator

entity accumulator is port ( -- definition of input and output terminals DI: in bit_vector(15 downto 0) -- a vector of 16 bit wide DO: inout bit_vector(15 downto 0); CLK: in bit ); end accumulator; architecture structure of accumulator is component reg -- definition of register ports port ( DI : in bit_vector(15 downto 0); DO : out bit_vector(15 downto 0); CLK : in bit ); end component; component add -- definition of adder ports port ( IN0 : in bit_vector(15 downto 0); IN1 : in bit_vector(15 downto 0); OUT0 : out bit_vector(15 downto 0) ); end component; -- definition of accumulator structure signal X : bit_vector(15 downto 0); begin add1 : add port map (DI, DO, X); -- defines port connectivity reg1 : reg port map (X, DO, CLK); end structure;
Design defined as composition of register and full-adder cells (netlist) Data represented as {0,1,Z} Time discretized and progresses with unit steps Description language: VHDL Other options: schematics, Verilog
Behavioral Description of Accumulator
entity accumulator is port ( DI : in integer; DO : inout integer := 0; CLK : in bit ); end accumulator; architecture behavior of accumulator is begin process(CLK) variable X : integer := 0; -- intermediate variable begin if CLK = '1' then X < = DO + D1; DO <= X; end if; end process; end behavior;
Design described as set of input-output relations, regardless of chosen implementation
Data described at higher abstraction level (integer)
Prentice Hall 1995
Behavioral simulation of accumulator

Discrete time
Integer data
(Synopsys Waves display tool)
Prentice Hall 1995
Timing Verification
Critical path
Enumerates and rank orders critical timing paths No simulation needed!
(Synopsys-Epic Pathmill)
Issues in Timing Verification
In 4-bit adder Out

MUX
False Timing Paths
bypass
Prentice Hall 1995
Implementation Methodologies
Digital Circuit Implementation Approaches
Custom Cell-Based
Semi-custom
Array-Based
Standard Cells Compiled Cells
Macro Cells
Pre-diffused (Gate Arrays)
Pre-wired (FPGA)
Prentice Hall 1995
Custom Design Layout Editor
Magic Layout Editor (UC Berkeley)

Symbolic Layout
VDD In 3 Out
Dimensionless layout entities Only topology is important Final layout generated by compaction program
1
GND
Stick diagram of inverter
Prentice Hall 1995
Cell-based Design (or standard cells)

Feedthrough Cell Logic Cell
Rows of Cells
Routing Channel
Routing channel requirements are reduced by presence of more interconnect layers
Functional Module (RAM, multiplier, )
Prentice Hall 1995
Standard Cell Example
[Brodersen92]
Standard Cell - Example
3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies
Prentice Hall 1995
Automatic Cell Generation
Random-logic layout generated by CLEO cell compiler (Digital)

Module Generators Compiled Datapath
bus0
mux reg0 reg1
bus2 bus1
routing area
feed-through
bit-slice
Advantages: One-dimensional placement/routing problem
buffer
Prentice Hall 1995
adder
Macrocell Design Methodology

Macrocell
Floorplan:
Defines overall topology of design, relative placement of modules, and global routes of busses, supplies, and clocks
Interconnect Bus
Routing Channel
Prentice Hall 1995
Macrocell-Based Design Example
SRAM
SRAM
Data paths
Standard cells
Video-encoder chip [Brodersen92]

Gate Array Sea-of-gates

polysilicon VD D
rows of uncommitted cells
metal GND possible contact
Uncommited Cell
In 1 In 2
In 3 In4
routing channel
Committed Cell (4-input NOR)

Out
Prentice Hall 1995
Sea-of-gate Primitive Cells

Oxide-isolation PMOS PMOS
NMOS
NMOS NMOS
Using oxide-isolation
Using gate-isolation
Prentice Hall 1995
Sea-of-gates
Random Logic
Memory Subsystem LSI Logic LEA300K (0.6 mm CMOS)

Prewired Arrays
Categories of prewired arrays (or fieldprogrammable devices): Fuse-based (program-once) Non-volatile EPROM based RAM based
Prentice Hall 1995
Programmable Logic Devices
PLA
PROM
PAL
Prentice Hall 1995
EPLD Block Diagram

Primary inputs
Macrocell
Courtesy Altera Corp.

Field-Programmable Gate Arrays Fuse-based

I/O Buffers Program/T est/Diagnostics V ertical routes
Standard-cell like floorplan

I/O Buffers I/O Buffers
I/O Buffers
Rows of logic modules Routing channels
Prentice Hall 1995
Interconnect
Programmed interconnection Input/output pin Cell Antifuse Horizontal tracks
Vertical tracks
Programming interconnect using anti-fuses

Field-Programmable Gate Arrays RAM-based

CLB CLB switching matrix Horizontal routing channel Interconnect point CLB CLB
Vertical routing channel
Prentice Hall 1995
RAM-based FPGA Basic Cell (CLB)

Combinational logic Storage elements R A B/Q1/Q2 C/Q1/Q2 D A B/Q1/Q2 C/Q1/Q2 D E Clock
Any function of up to 4 variables
Din
F
R D Q1 CE F G
Any function of up to 4 variables
R F G CE G D Q2
CE
Courtesy of Xilinx
RAM-based FPGA
Xilinx XC4025
Taxonomy of Synthesis Tasks

Architectural Level Logic Level Circuit Level
Behavioral View
state (i: 1..16) :: sum = sum*z1 + coeff[i]*In*z1 0 2 3 Architecture Synthesis Logic Synthesis 1
a b tp c x
Circuit Synthesis
Structural View
mem fsm *
a b c D x a b 2 2
4 1 c
Prentice Hall 1995
Design for Test
Prentice Hall 1995
Validation and Test of Manufactured Circuits

Goals of Design-for-Test (DFT)
Make testing of manufactured part swift and comprehensive
DFT Mantra
Provide controllability and observability
Components of DFT strategy

Provide circuitry to enable test Provide test patterns that guarantee reasonable coverage
Test Classification
Diagnostic test
used in chip/board debugging defect localization
go/no go or production test

Used in chip production
Parametric test
x e [v,i] versus x e [0,1] check parameters such as NM, Vt, tp, T
Prentice Hall 1995
Design for Testability

N inputs N inputs Combinational Logic Module K outputs Combinational Logic Module K outputs
M state regs (a) Combinational function (b) Sequential engine
2N patterns
2N+M patterns
Exhaustive test is impossible or unpractical

Problem: Controllability/Observability
Combinational Circuits:
controllable and observable - relatively easy to determine test patterns
Sequential Circuits: State!

Turn into combinational circuits or use self-test
Memory: requires complex patterns

Use self-test
Prentice Hall 1995
Test Approaches
Ad-hoc testing Scan-based Test Self-Test Problem is getting harder
increasing complexity and heterogeneous combination of modules in system-on-a-chip. Advanced packaging and assembly techniques extend problem to the board level
Prentice Hall 1995
Generating and Validating Test-Vectors
Automatic test-pattern generation (ATPG)

for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output majority of available tools: combinational networks only sequential ATPG available from academic research
Fault simulation
determines test coverage of proposed test-vector set simulates correct network in parallel with faulty networks
Both require adequate models of faults in CMOS integrated circuits

Fault Models
Most Popular - Stuck - at model
0 1
sa0 (output)
sa1 (input)
Covers almost all (other) occurring faults, such as opens and shorts.
Z
x1
x3
x2
, : x1 sa1 : x1 sa0 or x2 sa0 : Z sa1

Prentice Hall 1995
Problem with stuck-at model: CMOS open fault

x1 Z x1 x2 x2
Sequential effect
Needs two vectors to ensure detection! Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive!
Problem with stuck-at model: CMOS short fault

0 C D
Causes short circuit between Vdd and GND for A=C=0, B=1 Possible approach: Supply Current Measurement (IDDQ) but: not applicable for gigascale integration
Prentice Hall 1995
Path Sensitization
Goals: Determine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) 1 1 sa0 1 1 0
Out
Fault enabling
1 1 Fault propagation 0
Techniques Used: D-algorithm, Podem
Prentice Hall 1995
Ad-hoc Test
Memory
address data data
Memory
address
Prentice Hall 1995
test
select
Processor Processor
I/O bus I/O bus
Inserting multiplexer improves testability

Digital Integrated Circuits Design Methodologies
Scan-based Test
ScanIn ScanOut Out
Register
Logic A
Register
In
Combinational
Combinational Logic B
Prentice Hall 1995
Polarity-Hold SRL (Shift-Register Latch)

System Data D L1 Q SO Shift B Clock B L2 SO System Clock C SI Scan Data Shift A Clock A Q
Introduced at IBM and set as company policy

Scan-Path Register
OUT SCAN SCANIN PHI2 PHI1 SCANOUT
IN
LOAD
KEEP
Prentice Hall 1995
Scan-based Test Operation

In 0 Test ScanIn Latch Test Test In1 Test Test In2 Test Test In 3 Test ScanOut Latch Latch Latch
Out0
Out1
Out2
Out3
Test 1 2 N cycles scan-in

1 cycle evaluation
N cycles scan-out
Prentice Hall 1995
Scan-Path Testing
A REG[1] B REG[0] SCANIN REG[2] REG[3]
REG[4] COMPIN COMP
REG[5]
SCANOUT
Partial-Scan can be more effective for pipelined datapaths

OUT
Boundary Scan (JTAG)

Printed-circuit board Logic Packaged IC
normal interconnect
Scan-in Scan-out
si
so scan path
Bonding Pad
Board testing becomes as problematic as chip testing

Self-test
(Sub)-Circuit Stimulus Generator Under Test Response Analyzer
Test Controller
Rapidly becoming more important with increasing chip-complexity and larger modules
Linear-Feedback Shift Register (LFSR)

R S0 1 0 1 1 1 0 0 1 R S1 0 1 0 1 1 1 0 0 R S2 0 0 1 0 1 1 1 0
Pseudo-Random Pattern Generator

Signature Analysis
In Counter R
Counts transitions on single-bit stream Compression in time
Prentice Hall 1995
BILBO
B0 B1 ScanIn ScanOut R S0 R S1 R S2
mux
D0
D1
D2
B0 B1 1 0 1 0
Operation mode Normal Scan Pattern generation or Signature analysis Reset

1 0 0 1
BILBO Application
ScanIn ScanOut
BILBO-A
Logic
BILBO-B
In
Combinational
Combinational Logic
Out
Prentice Hall 1995
Memory Self-Test
data -in Memory FSM Under Test address & R/W control Analysis data-out Signature
Patterns: Writing/Reading 0s, 1s, Walking 0s, 1s Galloping 0s, 1s


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Design Methodologies

Digital Integrated Circuits

Prentice Hall 1995

The Design Problem

Design Analysis and Verification

Digital Integrated Circuits

Digital Data treated as Analog Signal

1.0 0 0.5 1 t (nsec) 1.5 2

Representing Data as Discrete Entity

Discretizing the data using switching threshold

The linear switch model of the inverter

Circuit versus Switch-Level Simulation

3.0 OUT[3] 1.0 1.0 0 5 10 15 time (nsec) 20

Prentice Hall 1995

Structural Description of Accumulator

Digital Integrated Circuits

Behavioral Description of Accumulator

Design described as set of input-output relations, regardless of chosen implementation

Data described at higher abstraction level (integer)

Digital Integrated Circuits

Prentice Hall 1995

Behavioral simulation of accumulator

(Synopsys Waves display tool)

Digital Integrated Circuits

Prentice Hall 1995

Enumerates and rank orders critical timing paths No simulation needed!

Issues in Timing Verification

In 4-bit adder Out

False Timing Paths

Digital Integrated Circuits

Prentice Hall 1995

Standard Cells Compiled Cells

Pre-diffused (Gate Arrays)

Digital Integrated Circuits

Prentice Hall 1995

Custom Design Layout Editor

Magic Layout Editor (UC Berkeley)

Prentice Hall 1995

Cell-based Design (or standard cells)

Functional Module (RAM, multiplier, )

Digital Integrated Circuits

Prentice Hall 1995

Standard Cell Example

Standard Cell - Example

Digital Integrated Circuits

Prentice Hall 1995

Automatic Cell Generation

Random-logic layout generated by CLEO cell compiler (Digital)

Module Generators Compiled Datapath

Advantages: One-dimensional placement/routing problem

Digital Integrated Circuits

Macrocell Design Methodology

Digital Integrated Circuits

Prentice Hall 1995

Macrocell-Based Design Example

Video-encoder chip [Brodersen92]

Gate Array Sea-of-gates

rows of uncommitted cells

metal GND possible contact

Committed Cell (4-input NOR)

Digital Integrated Circuits

Prentice Hall 1995

Sea-of-gate Primitive Cells

Digital Integrated Circuits