ECE 428 Programmable ASIC Design

Design Example:

A Simple SDRAM Tester

Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901

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Design Objectives
A simple testing procedure in which random numbers (generated by a LFSR)
are written into the SDRAM, and then read back to compare. A simple SDRAM controller that provides a SRAM-like interface No pipeline, no burst operation mode, not programmable

The SDRAM controller is modified from

XESS SDRAM controller application note The lecture also contain materials from Xilinx application notes XAPP174 and XAPP134

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Introduction to Delay-Locked Loop (DLL)

Delay-Locked Loop (DLL) and Phase-Locked Loop (PLL) are two types of components that used to remove clock skew. DLL and PLL also provide additional functionality:
Frequency synthesis: clock multiplication & clock division
Clock conditioning: duty cycle correction and phase shifting

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DLL & PLL Block Diagram

DLL

PLL

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Xilinx Spartan DLL Cell

Component symbol DLL output characteristics

Relation of output clocks

Output clk0 clk90 clk180 clk270 Phase shift (degree) 0 90 180 270 Period shift (%) 0 25% 50% 75%
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DLL Application Example

Standard Usage

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DLL Application Example

Application for removing both internal and external clock skew

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Introduction to SDRAM
SDRAMs are multi-bank DRAM arrays with a command-driven synchronous interface; Read and write access to SDRAMs are burst oriented

SDRAM pin description

Signal Name CS CLK CKE RAS Type Input Input Input Input Description Chip enable Clock Clock enable Row address strobe

CAS
WE DQML, DQMH BA

Input
Input Input Input

Column address strobe

Write enable Data Mask for lower, upper Bytes Bank address

A[10:0]
DQ[15:0]

Input
I/O

address
Data
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SDRAM Mode Register

Mode register is embedded in SDRAM. It defines SDRAM operation mode Mode register needs to be programmed via load mode command Mode register bit definition
Mode Register bits M[2:0] M[3] M[6:4] M[8:7] M9 M[11:10] # of bits 3 1 3 2 1 2 Description Burst length Burst type CAS latency Operation mode* Write burst mode Reserved for future use

* Normal operation mode is selected by setting M[8:7]=00. Other values are reserved for future use. Some SDRAMs do not support an operation mode choice. 14-9

Standard SDRAM Command

SDRAM commands are fed to SDRAM through pins: CS, RAS, CAS, WE BA A10 SDRAM command truth table

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SDRAM Access
Accessing an un-activated row
Clock
Command Address Activate Row address Read or Write Column address

Accessing an un-activated row

Clock Command Address Read or Write Column address

Column address does not take all address bits

Read or Write Column address

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Block Diagram of the Design

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CLKDLL Block Diagram

It also contain circuits that generate synchronized reset signal.

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Tester Block Diagram

randGen is an LFSR.

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TstCntl FSM

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More About State LOAD

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Verilog Coding for State Load

always @ (state) case state LOAD: // LOAD state if (~ack ) begin // wait for completing the previous write end else if (ack & not_last_write) begin // previous write complete // and not last write end else begin // previous write complete and last write end

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sdramcntl Block Diagram

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sdramcntl FSM

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sdramcntl Initialization States

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sdramcntl Refresh States

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sdramcntl Read & Write States

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More About State RW

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