On-Chip Interconnect Analysis and

Evaluation of Delay, Power, and

Bandwidth Metrics under Different
Design Goals

Introduction
Interconnect strategy, or interconnect planning has
become a critical part of chip design:
the growing significance of wire delay relative to gate delay .
increasing power consumption of wires: could be up to 50% of the total
dynamic power.
Influences the ASIC design methodology
Our work
Try to revamp the on-chip local interconnect
configuration for multi-objective optimization:

Compare different objective functions.
Formulate various matrics to measure the wire performance.
Identify the optimal wire configurations.

Evaluation Approach and Models
objective functions:



is the wire-length normalized delay.
is the wire-length-normalized power.

n
delay
n n
delay power
2
n n
delay power
n
delay
n
power
Evaluation Approach and Models
Metrics



is amount of data that can be transferred per unit
area per unit time.
n
delay
n
power
bandwidth / bandwidth power
( )
1/
n
bandwidth delay pitch =
Evaluation Approach and Models
Models
Elmore delay model:


Power model:


Leakage factor:



0 0
(1 )(1 )
(1 )
stage
nmos w
n w w inv w nmos inv
inv inv inv
d
b g f r c br c
delay ar c l b g r c s
l l s
+ +
= = + + + +
2
(1.1 )(1 )(1 )
stage
leak nmos inv
n w dd
inv inv
p
f g c s
power c v
l l
q | | + + +
= = +
|
\ .
Minimum Delay
Optimum repeater interval and size:



Optimum delay and power
Experimental results:
wire configuration
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-6
0
20
40
60
80
100
120
140
min-d
min-ddp
min-dp
pitch(m)
i
n
v
e
r
t
e
r

s
i
z
e
180nm
130nm
100nm
70nm
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-6
0
1
2
3
4
5
6
7
8
9
x 10
-7
min-d
min-ddp
min-dp
pitch(m)
w
i
d
t
h
(
m
)
180nm
130nm
100nm
70nm
Optimal inverter sizes Optimal widths
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-6
0
0.5
1
1.5
2
2.5
x 10
-3
pitch(m)
i
n
v
e
r
t
e
r

d
i
s
t
a
n
c
e
(
m
)
180nm
130nm
100nm
70nm
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-6
0
0.5
1
1.5
2
2.5
3
x 10
-3
pitch(m)
i
n
v
e
r
t
e
r

d
i
s
t
a
n
c
e
(
m
)
180nm
130nm
100nm
70nm
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-6
0
0.5
1
1.5
2
2.5
3
x 10
-3
pitch(m)
i
n
v
e
r
t
e
r

d
i
s
t
a
n
c
e
(
m
)
180nm
130nm
100nm
70nm
Optimal inverter distances in the min-dp procedure
Optimal inverter distances in the min-ddp procedure
Optimal inverter distances in the min-d procedure
Experimental results:
metric evaluation
50
100
150
200
0
0.5
1
1.5
x 10
-6
0
0.5
1
1.5
2
x 10
-7
te
c
h
n
o
d
e
p
it
c
h
(
m
)
d
e
l
a
y
n
(
s
/
m
)
min-d
min-ddp
min-dp
50
100
150
200
0
1
2
x 10
-6
0
1
2
3
4
5
6
x 10
-10
te
ch
n
o
d
e
p
i
t
c
h
(
m
)
p
o
w
e
r
(
J
/
m
)
min-d
min-ddp
min-dp
n
delay
n
power
50
100
150
200
0
0.5
1
1.5
x 10
-6
1
2
3
4
5
x 10
13
te
c
h
n
o
d
e
p
itc
h
(m
)
b
a
n
d
w
i
d
t
h
(
b
i
t
s
/
s
)
min-d
min-ddp
min-dp
50
100
150
200
0
0.5
1
1.5 x 10
-6
0
1
2
3
4
5
x 10
23
t
e
c
h
n
o
d
e
p
itc
h
(m
)
b
a
n
d
w
i
d
t
h
/
p
o
w
e
r
(
m
/
J
s
)
min-d
min-ddp
min-dp
Experimental results:
metric evaluation
bandwidth
/ bandwidth power