Sei sulla pagina 1di 19

LOGO

ANALOG ELECTRONICS II

Mohd Shawal Jadin

FET DC BIASING
Learning Objectives
Upon completion
1 of the chapter the student
should be able to:
2
1 Describe various configuration of FET biasing

Analyze various configuration of FET biasing.


2

ANALOG ELECTRONICS II - BEE2233 FKEE UMP


Introduction
 In FET, relationship between
input and output are not linear
that will sketched an output that
presenting a curve compared to
BJT where it is linear.
 Graphical approach will be used
to examine the dc analysis for
FET because it is most popularly
used rather than mathematical
approach
 The input of BJT and FET
controlling variables are the
current and the voltage levels
respectively
Overview
Common FET Biasing Circuits
 JFET
 Fixed – Bias

 Self-Bias

 Voltage-Divider Bias

 Depletion-Type MOSFET

 Self-Bias

 Voltage-Divider Bias

 Enhancement-Type MOSFET

 Feedback Configuration

 Voltage-Divider Bias
ANALOG ELECTRONICS II - BEE2233 FKEE UMP
General Relationships

For all FETs:
IG ≈ 0A ID = IS

For JFETs and Depletion­Type MOSFETs: 
VGS 2
ID = IDSS(1− )
VP

For Enhancement­Type MOSFETs:
I D = k (VGS −VT ) 2
Fixed-Bias Configuration

VS=0V

VGS = -VGG

VGS=VG - VS So: VG=VGS

VDS=VD - VS So: VD=VDS

Using KVL: VDS + IDRD - VDD. = 0

VDS= VDD - IDRD

ANALOG ELECTRONICS II - BEE2233 FKEE UMP


Investigating the input loop
IG=0A, therefore
 VRG=IGRG=0V
Applying KVL for the input loop,
 -VGG-VGS=0
 VGG=-VGS
It is called fixed-bias configuration
due to VGG is a fixed power supply so
VGS is fixed
VGS 2
I D = I DSS (1 −
The resulting current, )
VP
Investigating the graphical
approach..
Using below tables, we
can draw the graph

VGS ID
0 IDSS
0.3VP IDSS/2
0.5 IDSS/4
VP 0mA

The intersection of these points is


known as quiescent point/operating
point
Bear in mind…
Measured value in the circuit is
defined as the quiescent values
Example
Solution:
VGSQ , IDQ, VDS ,VD, VG ,VS.

VGSQ = -2V

IDQ = 5.625mA

VDS= VDD - IDRD = 4.75V.

VDS=VD - VS So: VD=VDS=4.75V.

VGS=VG - VS So: VG=VGS = - 2V

VS=0V

ANALOG ELECTRONICS II - BEE2233 FKEE UMP


Example

ANALOG ELECTRONICS II - BEE2233 FKEE UMP


Self­Bias Configuration
What is the differences between self bias configuration and fixed-bias
configuration?

Why when analyzing dc analysis the resistor RG will be replaced by a short


circuit equivalence?
Self­Bias Calculations 

For the indicated input loop:  VGS = −I D R S

To draw or sketch and analyzing the graphical approach of this configuration,
 To solve this equation select an ID < IDSS and use the component value for RS. 
Plot this point: ID and VGS and draw a line from the origin of the axis to this point.
Next plot the transfer curve using IDSS and VP (VP = VGSoff in specification sheets) and a 
few points such as ID = IDSS/4 and ID = IDSS/2 etc.

Where the first line intersects the transfer curve is the Q­point.

Use the value of ID at the Q­point (IDQ) to solve for the other voltages:

The output loop:  VDS = VDD − I D ( RS + RD )


VS = I D RS
VD = VDS + VS = VDD − VRD
Defining Q­point 
Check your understanding..
Find IDQ, VGSQ and IDSS
Check your understanding..
Find ID and VDS
LOGO

Mohd Shawal Jadin

Potrebbero piacerti anche