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ANALOG ELECTRONICS II
FET DC BIASING
Learning Objectives
Upon completion
1 of the chapter the student
should be able to:
2
1 Describe various configuration of FET biasing
Self-Bias
Voltage-Divider Bias
Depletion-Type MOSFET
Self-Bias
Voltage-Divider Bias
Enhancement-Type MOSFET
Feedback Configuration
Voltage-Divider Bias
ANALOG ELECTRONICS II - BEE2233 FKEE UMP
General Relationships
For all FETs:
IG ≈ 0A ID = IS
For JFETs and DepletionType MOSFETs:
VGS 2
ID = IDSS(1− )
VP
For EnhancementType MOSFETs:
I D = k (VGS −VT ) 2
Fixed-Bias Configuration
VS=0V
VGS = -VGG
VGS ID
0 IDSS
0.3VP IDSS/2
0.5 IDSS/4
VP 0mA
VGSQ = -2V
IDQ = 5.625mA
VS=0V
For the indicated input loop: VGS = −I D R S
To draw or sketch and analyzing the graphical approach of this configuration,
To solve this equation select an ID < IDSS and use the component value for RS.
Plot this point: ID and VGS and draw a line from the origin of the axis to this point.
Next plot the transfer curve using IDSS and VP (VP = VGSoff in specification sheets) and a
few points such as ID = IDSS/4 and ID = IDSS/2 etc.
Where the first line intersects the transfer curve is the Qpoint.
Use the value of ID at the Qpoint (IDQ) to solve for the other voltages: