DELAY MODELS

Concurrent versus Sequential Execution

architecture CONCURRENT of MULTIPLE
is
signal A, B, C, D : std_ulogic;
signal Z : std_logic
begin
Z <= A and B;
Z <= C and D;
end CONCURENT
architecture SEQUENTIAL of MULTIPLE is
signal Z, A, B, C, D : std_ulogic;
begin
process (A, B, C, D)
begin
Z <= A and B;
Z <= C and D;
end process;
end SEQUENTIAL;
• If the same two signal assignments appear
in the VHDL code, once as concurrent
statement in the architecture and once in a
process, the result will differ substantially:
In the first case, two parallel signal
assignments are actually made to the signal.
This is only allowed for resolved types, for
which a resolution functions is present to
decide which value is actually driven..
• In the second case, the first assignment is
executed and its result is stored. Afterwards,
this result is overwritten by another
assignment, so that only the last signal
assignment is carried out when updating the
signal
 Signal Update

• Signals have a past value, a current value and a

future value
• future value used within the simulator core, only
• past value ≠ current value: event
• Signal values are updated at the end of a process
execution:
• the old current value of a signal is overwritten by
the future value
• Several process calls at one single moment of the
simulation are possible
 Process Behaviour
• The process is an endless loop
• It is stopped by a wait-statement
• The sensitivity list is equivalent to a wait-
statement
• A process with a sensitivity list must not
contain any wait statements
process (A, B)
begin
if (A=B) then
Z <= `1`;
else
Z <= `0`;
end if;
end process;
process
begin
if (A=B) then
Z <= `1`;
else
Z <= `0`;
end if;
wait on A, B;
end process;
• The three delay models are
• a) Transport Delay model
• b) Inertial Delay model
 Delay Models

• Transport delay:

• models the current flow through a wire

• (everything is transferred)
 Inertial delay: (default delay
mechanism)

• models spike-proof behavior => a value is

transferred only if it is active for at least the
pulse rejection limit.
• Z<=reject 4ns inertial A after 10 ns;
• S<= A after 2 ns;
• Inertial delay with pulse rejection limit

• models spike-proof behaviour => a value is

transferred only if it is active for at least the
pulse rejection limit.
• There are two different delay models in
VHDL: transport and inertial, which is used
per default.

• In the transport delay model, everything is

transferred via the signal, as can be seen in
the upper example where signal A is an
exact copy of signal S, delayed by 2 ns.
Transport delay models signal transfers by
wire with pure propagation delay, thus
spikes are not filtered out.
 INERTIAL DELAY
• When using inertial delay, signal transitions
are only transferred when the new value
remains constant for a minimum amount of
time, thus spikes are suppressed.
• Inertial delay is characteristic of switching
circuits. Spikes which are shorter than the
necessary specific switching time of the
circuit have no effect on the succeeding
switch and will not be transmitted.
• As conclusion, all signal assignments can
be brought into the following format:
• T <= reject TIME_1 inertial VALUE after
TIME_2;
• The following assignments are equivalent:
• T <= VALUE after TIME_1; -- (default
inertial delay)
• T <= inertial VALUE after TIME_1;
• T <= reject TIME_1 inertial VALUE after
TIME_1;
• Also equivalent are:
• T <= transport VALUE after TIME_1;
• T <= reject 0 ns inertial VALUE after
TIME_1;

• Furthermore "T <= VALUE" is just a

shortcut for "T <= VALUE after 0 ns".
 Signal Drivers

• Issues when more than one assignment to a signal within a

process
A <= 3 after 10 ns, 5 after 15 ns, 7 after 20 ns;
--------
A <= 9 after 12 ns, 11 after 18 ns;

• A signal driver is created for every signal that is assigned a

value inside a process;

• A signal driver holds current value and future values as a

sequence of one or more transactions
 Signal Drivers

A <= 3 after 10 ns, 5 after 15 ns, 7 after 20 ns;

Curr@now 3@ 10 ns 5@ 15 ns 7@ 20 ns

A <= 9 after 12 ns, 11 after 18 ns;

• Only one driver for a signal inside a process

• The transactions are deleted and/or added depending on which

delay model is being used
 Signal Drivers for Transport Delay

• When a new signal assignment is executed, all old transactions

after the new delay is deleted
• All new transactions are added to the driver

A <= TRANSPORT 3 after 10 ns, 5 after 15 ns, 7 after 20 ns;

Curr@now 3@ 10 ns 5@ 15 ns 7@ 20 ns

A <= TRANSPORT 9 after 12 ns, 11 after 18 ns;

Curr@now 3@ 10 ns 9@ 12 ns 11@ 18 ns
 Signal Drivers for Inertial Delay

• When a new signal assignment is executed, all old transactions

after the new delay is deleted
• If there is a different transaction in the time range F to F- PRL,
its deleted. Else its maintained (F : delay of new assignment)
• All new transactions are added to the driver

A <= 3 after 10 ns, 5 after 15 ns, 7 after 20 ns;

Curr@now 3@ 10 ns 5@ 15 ns 7@ 20 ns

A <= REJECT 5 NS INERTIAL 9 after 12 ns, 11 after 18 ns;

Curr@now 9@ 12 ns 11@ 18 ns
process
begin
A-Bus <= 1 after 5 ns, 21 after 9 ns, 6 after
10 ns;
A-Bus<= reject 4 ns inertial 6 after 12 ns ,20
after 19 ns ;
Wait;
End process;
The status after the first statement is

curr@now 1@5ns 21@9ns 6@10ns 12@19ns

• The execution of the second statement
causes all transactions on the driver later
than 12 ns (the inertial delay of first
waveform) to be deleted ,which would be
12 @19 ns transaction .The two new
transactions 6@12ns and 20 @ 19 ns ,are
added to the driver.The old transaction 21
@ 9ns also gets deleted since its delay falls
in the window of time 12ns and (12ns-4ns)
and its value (which is 21) ,is not the same
as the value of the first new transaction
(which is 6)
 Transport Delay (1)
signal S : integer := 0;
process
begin
S <= transport 1 after 1 ns;
S <= transport 2 after 2 ns;
wait;
end process;
signal S : integer := 0;
process
begin
S <= transport 2 after 2 ns;
S <= transport 1 after 1 ns;
wait;
end process;
• A signal driver manages value/time pairs
• It is not possible to assign a new value for
Timei < Timei-1
• Within a signal driver, the actual values are
always associated with an activation time.
The initial value/time (0, 0 ns) pair for the
integer signal of the example is left out in
the figures as this pair remains unaffected at
any time.
 Transport Delay (2)

signal S : integer := 0;
process
begin
S <= transport 1 after 1 ns, 3 after 3 ns, 5 after 5 ns;
S <= transport 4 after 4 ns;
wait;
end process;
signal S : integer := 0;
process
begin
S <= transport 1 after 1 ns, 3 after 3 ns, 5 after 5 ns;
S <= transport 4 after 6 ns;
wait;
end process;
 Inertial Delay

signal S : integer := 0;
process
begin
S <= 1 after 1 ns;
S <= 2 after 2 ns;
wait;
end process;
signal S : integer := 0;
process
begin
S <= 1;
S <= 2;
wait;
end process;
S <= 1; -- equivalent to
S <= 1 after 0 ns;
signal S : integer := 0;
process
begin
S <= 2 after 2 ns;
S <= 1 after 1 ns;
wait;
end process;
signal S : integer := 0;
process
begin
S <= 1 after 2 ns;
S <= 1 after 1 ns;
wait;
end process;
• The last assignment to a signal in a process
takes effect
Inertial Delay (2)
• Inertial Delay (3)

signal S : integer := 0;
process
begin
S <= 2 after 3 ns, 2 after 12 ns, 12 after 13 ns,
5 after 20 ns, 8 after 42 ns;
S <= reject 15 ns inertial 12 after 20 ns, 18
after 41 ns;
wait;
end process;