VHDL CONCEPTS

Execution of assignments:

• Sequential -
• Concurrent-order is not important
 Methodologies:

• Abstraction-
• Modularity
• Hierarchy
 ABSTRACTION
Abstraction allows for the description of
different parts of a system with different
amount of detail.
Modules which are needed only for the
simulation do not have to be described as
detailed as modules that might be
synthesized.
 MODULARITY

• Modularity enables the

designer(s) to split big
functional blocks and to
write a model for each part
 HIERARCHY
• Hierarchy lets the designer build a design
out of submodules which may consist of
several submodules, themselves.
• Each level of hierarchy may contain
modules of different abstraction levels.
• The submodules of these models are
present in the next lower hierarchical level.
 ABSTRACTION
• Abstraction is hiding of details:
• Differentiation between essential and
nonessential information

•
• Creation of abstraction levels:
• On every abstraction level only the
essential information is considered,
nonessential information is left out
 BEHAVIOURAL
• This is the functional description
• no system clock
• signal transitions are asynchronous with
respect to the switching time.
• Usually, such descriptions are simulatable,
only, but not synthesizable.
 RTL
• In the next step, the design is divided into
combinational logic and storage elements.
• This is called the Register Transfer Level
(RTL). The storage elements (Flip Flops
(FFs), latches) are controlled by a system
clock.
 RTL
• In synchronous designs, FFs should be
used (driven by the edge of the clock
signal) exclusively, because transparent
latches (driven by the level of a control
signal) are not spike-proof
 SYTHESIZABLE
• For the description on RT level only 10 to
20 percent of all VHDL language
constructs are needed and a strict
methodology has to be followed. This
description on RT level is called
synthesizable description.
 LOGIC LEVEL
• On the logic level, the design is
represented as a netlist with logic gates
(AND, OR, NOT, ...) and storage
elements.
 LAYOUT
• The different cells of the target technology
are placed on the chip and the
connections are routed. After the layout
has been verified, the circuit is ready for
the production process.
 VHDL
• Suited only for upper three levels
• But all levels are automated
• Placement and route has also been
automated
 SPECIFICATIONS
• The output o depends upon the three
input values i1, i2 and i3.
• Furthermore it is specified that a new
output value must be stable at the latest
100 ns after the input values have
changed.
BEHAVIOURAL DESCRIPTION
• The function can be modeled as a simple
equation (eg. i1 + i2 * i3) plus a delay of
100 ns.
• The worst case, i.e. that 100 ns are
needed to calculate a new output value, is
assumed here.
 Behavioral level
• Processes model functional behaviour
 RT level processes -2 types
• The pure combinational process
• and the clocked process.
• All clocked processes infer FlipFlops and
can be described in terms of state
machine syntax.
 Gate Level in VHDL
• A VHDL gate level description contains a
list of the gates (components) that are
used in the design.
• Another part holds the actual instantiation
of the components and lists their
interconnection.
 Behavioral
• The behaviour model is a simple way to
describe the behaviour of a circuit, similar
to usual software programming languages,
such as PASCAL or C.
• With this description, only the functional
behaviour can be simulated by a VHDL
simulator.
 RT Level Description
• The clock pulse is the distinguishing mark
for the RT level description.
• All operations are related to the clock
signal.
• RT level simulations give no information
about the real timing behaviour, which
means that is impossible to tell, whether
all signals have actually settled to stable
values within one clock period or not.
 Logic Level
• When the model is described on the logic level,
delays can be applied to the used gates for
simulation.
• The timing information is part of the
synthesis library. This enables a rough
validation of the timing behaviour.
• The uncertainty stems from the propagation
delay along the signal wires which has not yet
been considered. These delays may very well
make up the main part of the entire delay in
larger designs.
 LAYOUT
• If the layout is completed, the wire lengths
and thus the propagation delays will be
known.
• The design can be simulated on gate level
with the additional delay values and
consequently the timing behaviour of the
entire circuit can be validated.
 Timing Simulation
• Yet, the simulation time grows
considerably with the increased amount of
information about the circuit, which
restricts timing simulation to small parts of
complex designs.