FPGAs

ENEE 245
FPGA Devices and FPGA Design Flow
ENEE 245 Digital Circuits and Systems Laboratory
Outline
Programmable Logic Devices
Basics Evolution
Field Programmable Gate Arrays (FPGAs)

Architecture
Design Flow
Hardware Description Languages Design Tools
Standard Chips
Small number of transistors (< 100) Simple and fixed functions Logic designer must decide how to interconnect multiple chips for desired function Agreed upon / standard functionality Popular in the 1980s too large in physical size for much industry use now (good for teaching though!)
3
7400 Series TTL Logic Chips

The 7400 NAND Chip: pin layout
1 2 3 4 5 6 Gnd 7 7400
14 13 12 11 10 9 8
Vcc = +5V
The equivalent logic layout

00
1 2 3
4 5
9 10
12 13
11
Discrete Logic Implementation

Digital Logic Function 3 Inputs Product AND (&) Sum OR (|)
Black Box
Truth Table
SUM of PRODUCTS Boolean Logic Minimization
Connect Standard Logic Chips Very Simple Glue Logic FIXED Logic
Discrete Logic Implementation

Digital circuits may be implemented as discrete circuits using many standard chips interconnected on
A breadboard A printed circuit board (PCB)
Implementing With 7400 Series

Implementing f = x1x2 + x2'x3
V DD
7404
7408
7432
x1 x2 x3
f
7
Discrete Circuits - Only For Small Systems!
Programmable Logic Devices PLDs

Different Types SUM of PRODUCTS Prefabricated Programmable Links Reconfigurable
Inputs ANDs OR Un-programmed State Planes of ANDs, ORs
Logic Function
Sums
Programmed PLD Product Terms Sum of Products
Two competing implementation approaches

ASIC Application Specific Integrated Circuit
Designed all the way from behavioral description to physical layout Designs must be sent for expensive and time consuming fabrication in semiconductor foundry
FPGA Field Programmable Gate Array

No physical layout design; design ends with a bitstream used to configure a device
Bought off the shelf and reconfigured by designers themselves

10
Which Way to Go?

ASICs FPGAs
Off-the-shelf
High performance Low development cost Low power Short time to market Low cost in high volumes
Reconfigurability
11
Why use Programmable Chips?

As compared to hard-wired chips, programmable chips can be customized as per needs of the user by programming This convenience, coupled with the option of reprogramming in case of problems, makes the programmable chips very attractive Other benefits include instant turnaround, low starting cost and low risk
12
Field-Programmable Gate Arrays

Logic blocks to implement combinational and sequential logic wires to connect inputs and outputs to logic blocks
Interconnect
I/O blocks
special logic blocks at periphery of device for external connections
Key questions: how to make logic blocks programmable? how to connect the wires? after the chip has been fabbed
13
Field Programmable Gate Arrays

Field Programmable Gate Array New Architecture Simple Programmable Logic Blocks Massive Fabric of Programmable Interconnects Large Number of Logic Block Islands 1,000 100,000+ in a Sea of Interconnects
FPGA Architecture
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Logic Blocks
Logic Functions implemented in Lookup Table LUTs Multiplexers (select 1 of N inputs) Flip-Flops. Registers. Clocked Storage elements.
16-bit SR 16x1 RAM 4-input LUT
a b c d e
mux flip-flop q
clock clock enable set/reset
FPGA Fabric
Logic Block
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Lookup Tables LUTs

LUT contains Memory Cells to implement small logic functions Each cell holds 0 or 1 . Programmed with outputs of Truth Table Inputs select content of one of the cells as output
3 Inputs LUT -> 8 Memory Cells
16-bit SR 16x1 RAM 4-input LUT
3 6 Inputs
a b c d e
y mux flip-flop q
clock clock enable set/reset

SRAM
SRAM
Multiplexer MUX
Static Random Access Memory SRAM cells
16
Routing
Connections Routing signals between Logic Blocks Determined by SRAM cells
SRAM
Special Routing for Clocks
Around Fabric Edges Configurable Input Output I/O Blocks 100s 1,000 Pins
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Applications of FPGAs
Implementation of random logic easier changes at system-level (one device is modified) can eliminate need for full-custom chips Prototyping ensemble of gate arrays used to emulate a circuit to be manufactured get more/better/faster debugging done than possible with simulation Reconfigurable hardware one hardware block used to implement more than one function functions must be mutually-exclusive in time can greatly reduce cost while enhancing flexibility RAM-based only option Special-purpose computation engines hardware dedicated to solving one problem (or class of problems) accelerators attached to general-purpose computers
18
FPGA vendors and FPGA families
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Technology Timeline
1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000 Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs FPGAs
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Major FPGA vendors

SRAM-based FPGAs Xilinx Inc. www.xilinx.com Altera Corp. www.altera.com Atmel Corp. www.atmel.com Lattice Semiconductor Corp. www.latticesemi.com Antifuse and flash-based FPGAs Actel Corp. www.actel.com QuickLogic Corp. www.quicklogic.com
ENEE 245 Digital Circuits and Systems Laboratory 21
The Programmable Marketplace

Q1 Calendar Year 2005
PLD Segment Actel Lattice 5% 7% FPGA Sub-Segment
QuickLogic: 2% Other: 2%
Xilinx
58% 33% 51% 31% Altera 11%
Xilinx
Altera
All Others
Two dominant suppliers, indicating a maturing market

Source: Company reports Latest information available; computed on a 4-quarter rolling basis
22
FPGA Families
Low-cost High-performance
Virtex 4 LX / SX / FX Virtex 5 LX
Xilinx
Spartan 3 Spartan 3E Spartan 3L
Altera
Cyclone II
Stratix II Stratix II GX
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Xilinx FPGAs
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Xilinx
Primary products: FPGAs and the associated CAD software
Programmable Logic Devices
ISE Alliance and Foundation Series Design Software
Main headquarters in San Jose, CA Fabless* Semiconductor and Software Company UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996} Seiko Epson (Japan) TSMC (Taiwan) Source: [Xilinx Inc.]
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Xilinx FPGA Families

Old families XC3000, XC4000, XC5200 Old 0.5m, 0.35m and 0.25m technology. Not recommended for modern designs. Low Cost Family Spartan/XL derived from XC4000 Spartan-II derived from Virtex Spartan-IIE derived from Virtex-E Spartan-3, Spartan 3E, Spartan 3L High-performance families Virtex (220 nm) Virtex-E, Virtex-EM (180 nm) Virtex-II, Virtex-II PRO (130 nm) Virtex-4 (90 nm) Virtex 5 (65 nm)
Source: [Xilinx Inc.]
26
Xilinx FPGA Prices

Low-cost High-performance
Spartan 3 < $130* Spartan 3E < $35*
Virtex II, Virtex II-Pro < $3,000* Virtex 4 < $3,000*
* approximate cost of the largest device per unit for a batch of 10,000 units
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Xilinx FPGA
Configurable Logic Blocks
Block RAMs Block RAMs
I/O Blocks Block RAMs
28
Xilinx CLB
Configurable logic block (CLB) Slice CLB CLB Logic cell Logic cell Slice Logic cell Logic cell
Slice CLB CLB Logic cell Logic cell
Slice Logic cell Logic cell
29
Simplified view of a Xilinx Logic Cell

16-bit SR 16x1 RAM
a b c d e clock clock enable set/reset
4-input LUT
y mux flip-flop q
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LUT (Look-Up Table) Functionality

x1 x2 x3 x4 y
x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
x2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
x3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
x4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
y 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
LUT
x1 x2 x3 x4
x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
x2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
x3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
x4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
y 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0
Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs
x1 x2 y y
31
5-Input Functions implemented using two LUTs

X 5 X 4 X 3 X 2 X 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 Y 0 1 0 0 1 1 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0
LUT
OUT
LUT
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Carry & Control Logic

COUT YB G4 G3 G2 G1 Y Look-Up O Table S
D CK EC
F5IN BY SR XB
F4 F3 F2 F1
X Look-Up Table O
S D CK EC R Q
CIN CLK CE
SLICE
33
Fast Carry Logic
Each CLB contains separate logic and routing for the fast generation of sum & carry signals
Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters
MSB
Carry Logic Routing LSB
34
Carry logic is independent of normal logic and routing resources
CLB Slice Structure

Each slice contains two sets of the following:
Four-input LUT
Any 4-input logic function, or 16-bit x 1 sync RAM (SLICEM only) or 16-bit shift register (SLICEM only)
Carry & Control

Fast arithmetic logic Multiplier logic Multiplexer logic
Storage element
Latch or flip-flop Set and reset True or inverted inputs Sync. or async. control
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Block RAM
Port B Port A
Spartan-3 Dual-Port Block RAM
Block RAM
Most efficient memory implementation

Dedicated blocks of memory
Ideal for most memory requirements

4 to 104 memory blocks
18 kbits = 18,432 bits per block (16 k without parity bits)
Use multiple blocks for larger memories
Builds both single and true dual-port RAMs

Basic I/O Block Structure

Three-State FF Enable Clock Set/Reset Output FF Enable D Q EC SR Direct Input FF Enable Input Path
D Q EC SR
Three-State Control
Output Path
Registered Input
D EC
SR
37
IOB Functionality
IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into high impedance Inputs and outputs can be registered
advised for high-performance I/O
Inputs can be delayed

FPGA Design Flow
Computer-Aided Design
Can't design FPGAs by hand Way too much logic to manage, hard to make changes Hardware description languages Specify functionality of logic at a high level Validation: high-level simulation to catch specification errors Verify pin-outs and connections to other system components Low-level to verify mapping and check performance Logic synthesis Process of compiling HDL program into logic gates and flipflops Technology mapping Map the logic onto elements available in the implementation technology (LUTs for Xilinx FPGAs)
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CAD Tool Path (contd)

Placement and routing Assign logic blocks to functions Make wiring connections Timing analysis - verify paths Determine delays as routed Look at critical paths and ways to improve Partitioning and constraining If design does not fit or is unroutable as placed split into multiple chips If design it too slow prioritize critical paths, fix placement of cells, etc. Few tools to help with these tasks exist today Generate programming files - bits to be loaded into chip for configuration
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Design Process (1)

Specification
Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds..
Verilog description (Your Source Files)

Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core;
Functional simulation
Synthesis
Post-synthesis simulation
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Design Process (2)

Implementation (Translating, Mapping, Placing & Routing) Timing simulation
Configuration On chip testing
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Logic Synthesis
HDL description
architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW;
Circuit netlist
44
Synthesis Tools
and others
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Implementation
After synthesis the entire implementation process is performed by FPGA vendor tools
46
47
Mapping
LUT0
LUT4 LUT1
LUT5 LUT2 FF2 LUT3 FF1
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Placing
FPGA
CLB SLICES
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Routing
Programmable Connections
FPGA
50
Map Report
Design Summary -------------Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 144 out of 4,704 3% Number of 4 input LUTs: 173 out of 4,704 3% Logic Distribution: Number of occupied Slices: 145 out of 2,352 6% Number of Slices containing only related logic: 145 out of 145 100% Number of Slices containing unrelated logic: 0 out of 145 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 210 out of 4,704 4% Number used as logic: 173 Number used as a route-thru: 5 Number used as 16x1 RAMs: 32 Number of bonded IOBs: 74 out of 176 42% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25
Place & Route Report

Timing Score: 0 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. -------------------------------------------------------------------------------Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------TS_clk = PERIOD TIMEGRP "clk" 11.765 ns | 11.765ns | 11.622ns | 13 HIGH 50% | | | -------------------------------------------------------------------------------OFFSET = OUT 11.765 ns AFTER COMP "clk" | 11.765ns | 11.491ns | 1 -------------------------------------------------------------------------------OFFSET = IN 11.765 ns BEFORE COMP "clk" | 11.765ns | 11.442ns | 2 --------------------------------------------------------------------------------
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Post Layout Timing Report

Timing summary: --------------Timing errors: 0 Score: 0
Constraints cover 42912 paths, 0 nets, and 1038 connections

Design statistics: Minimum period: 11.622ns (Maximum frequency: 86.044MHz) Minimum input required time before clock: 11.442ns Minimum output required time after clock: 11.491ns
Configuration
Once a design is implemented, you must create a file that the FPGA can understand
This file is called a bit stream: a BIT file (.bit extension)
The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information
54
Configuration of SRAM based FPGAs

Configuration data in Configuration data out
= I/O pin/pad = SRAM cell
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ENEE 245

FPGA Devices and FPGA Design Flow

ENEE 245 Digital Circuits and Systems Laboratory

Field Programmable Gate Arrays (FPGAs)

7400 Series TTL Logic Chips

The equivalent logic layout

Discrete Logic Implementation

SUM of PRODUCTS Boolean Logic Minimization

Discrete Logic Implementation

Implementing With 7400 Series

Discrete Circuits - Only For Small Systems!

Programmable Logic Devices PLDs

Programmed PLD Product Terms Sum of Products

Two competing implementation approaches

FPGA Field Programmable Gate Array

Bought off the shelf and reconfigured by designers themselves

Which Way to Go?

ENEE 245 Digital Circuits and Systems Laboratory

Why use Programmable Chips?

Field-Programmable Gate Arrays

special logic blocks at periphery of device for external connections

Field Programmable Gate Arrays

clock clock enable set/reset

Lookup Tables LUTs

clock clock enable set/reset

Static Random Access Memory SRAM cells

Special Routing for Clocks

FPGA vendors and FPGA families

ENEE 245 Digital Circuits and Systems Laboratory

ENEE 245 Digital Circuits and Systems Laboratory

Major FPGA vendors

The Programmable Marketplace

58% 33% 51% 31% Altera 11%

Two dominant suppliers, indicating a maturing market

ENEE 245 Digital Circuits and Systems Laboratory

Spartan 3 Spartan 3E Spartan 3L

ENEE 245 Digital Circuits and Systems Laboratory

ENEE 245 Digital Circuits and Systems Laboratory

Primary products: FPGAs and the associated CAD software

Programmable Logic Devices

ISE Alliance and Foundation Series Design Software

ENEE 245 Digital Circuits and Systems Laboratory

Xilinx FPGA Families

ENEE 245 Digital Circuits and Systems Laboratory

Xilinx FPGA Prices

Spartan 3 < $130* Spartan 3E < $35*

Virtex II, Virtex II-Pro < $3,000* Virtex 4 < $3,000*

ENEE 245 Digital Circuits and Systems Laboratory

I/O Blocks Block RAMs

ENEE 245 Digital Circuits and Systems Laboratory

Slice CLB CLB Logic cell Logic cell

Slice Logic cell Logic cell

ENEE 245 Digital Circuits and Systems Laboratory

Simplified view of a Xilinx Logic Cell

a b c d e clock clock enable set/reset

ENEE 245 Digital Circuits and Systems Laboratory

LUT (Look-Up Table) Functionality

ENEE 245 Digital Circuits and Systems Laboratory

5-Input Functions implemented using two LUTs

ENEE 245 Digital Circuits and Systems Laboratory

Carry & Control Logic

Carry & Control Logic

Carry & Control Logic

ENEE 245 Digital Circuits and Systems Laboratory