Constellations DAC09 Presentation

SoC Democratization
PowerPoint to Silicon
Jim Hogan - DAC 2009

System Perspective
“We don’t want our engineers writing Verilog,

we want them inventing concepts and
transferring them into silicon and SW using
automated processes.”
Yoshihito Kondo – General Manager

Design Platform Division
The SoC Battleground
System
Applications
Collaborate to Innovate
Firms will increasingly look outside their walls not just to
reduce costs but for INNOVATION – in processes,
product and service differentiation – to free up resources,
transform their businesses, and facilitate sustainable
competitive advantage. As supply networks become
more global and complex, winning will depend on
transparency, trustworthiness, and reciprocity. In a word:
COLLABORATION.
Source: Alan McCormack et al. HBS
The ideal collaboration model is the VIRTUAL

CORPORATION where the different firms involved in
collaboration act as if they were division of the same
corporation (or even better!!).
Source: Dr. Alberto Sangiovanni-Vincentelli
SoC Asset-lite Platform World
• Will
• Utilize SoCs to integrate system application
knowledge and capturing the user experience Multi-Processor SoC
• Capture more value than a standard discrete
component
• How?
Custom
• Deploy heterogeneous multiple processors running CPU DSP
DSP
their own distinct hardware operating software
• Focus
• Core competencies in architecture and software
• SoC integration
• Shed the need for ongoing investment in ubiquitous
design and commoditized assets such as I/O I/O I/O
standardized intellectual property (USB, PCI,
DDR…) FPGA
FPGA eMEM
Periph MEM
• Ecosystem partnerships in non-differentiated IP,
physical implementation, foundry and test
Chip design has moved from

Feature Differentiation to Optimization
The SoC Design Integration Nightmare
Specification:
Implementation:
P. Picasso,
Blue Period
P. Picasso
“Femme se
coiffant”
1940
Proof Point of a Flexible Integration Platform
Wireless Application Processors
Debug TI OMAP 3 platform architecture
• Up to 4 heterogeneous processors
• Over 100 peripherals
• Aggressive power requirements
OMAP 3
Collaboration challenges
SONICS Interconnect
ARM MPEG • Teams spread across 3 continents

• Many IP suppliers
Image
3D GFX Processing – ARM, Imagination, Mentor Graphics,
Sonics, Synopsys, TI …
Data Internal
Movers Memory Integration platform solutions
• Socket-based IP integration using OCP
Event and Sonics’ communication networks
Handlers Security
W-
CDMA • Architecture sign-off at SystemC
• Early/automated integration and physical
implementation trials
• Automated system verification
[Source: Texas Instruments]

Collaborating to Create the iPhone
SAMSUNG ST MICRO INFINEON SKYWORKS
Application LIS331 DL SP3i SKY77340
SST Processor andAccelerometer SMARTi Power
Power Amp. Module
SST25VF080B DDR SDRAM Management IC INFINEON
1 MB Serial Flash UMTS Transceiver
NATIONAL TRIQUINT
SEMICONDUCTOR TQM666032
LM2512AA WCDMA/HSUPA
Display Interface Power Amp.
TRIQUINT
TQM676031
BROADCOM WCDMA/HSUPA
BCM5974 Power Amp.
Touchscreen
Controller TRIQUINT
TQM616035
WCDMA/HSUPA
Power Amp.
INFINEON
WOLFSON Digital Baseband
WM6180C Processor
Audio Codec
INFINEON LINEAR TECH NXP NUMONYX

PMB2525 LTC4088-2 Power PF38F3050M0Y0CE
Hammerhead II Battery Charger/ Management 16 MB NOR + 8 MB
GPS USB Controller Pseudo - SRAM

Collaborating to Create the iPhone
INFINEON Digital Baseband Processor
SAMSUNG ST MICRO INFINEON SKYWORKS
Application LIS331 DL SMP3i SKY77340
Processor and Accelerometer SMARTi Power
Power Amp. Module
SST DDR SDRAM Management IC INFINEON
SST25VF080B UMTS Transceiver
1 MB Serial Flash
NATIONAL TRIQUINT
SEMICONDUCTOR TQM666032
LM2512AA WCDMA/HSUPA
Display Interface Power Amp.
TRIQUINT
TQM676031
BROADCOM WCDMA/HSUPA
BCM5974 Power Amp.
Touchscreen
Controller TRIQUINT
TQM616035
WCDMA/HSUPA
Power Amp.
INFINEON
WOLFSON Digital Baseband
WM6180C Processor
Audio Codec
INFINEON LINEAR TECH NXP NUMONYX

PMB2525 LTC4088-2 Power PF38F3050M0Y0CE
Hammerhead II GPS Battery Charger/ Management 16 MB NOR + 8 MB
USB Controller Pseudo - SRAM

Collaboration requires Standardization

What is required to design an optimized SOC?
Standardization at the Right Level of Abstraction
Architecture SoC Platform signoff
RTL/Logic Functional signoff
Synthesis Netlist Timing signoff
Custom Foundry Transistor Model
. Source: Dr. Alberto Sangiovanni-Vincentelli

Green Field Opportunity
• Abstraction Layer must move sign-off from logic netlist or RTL
to SoC Platform signoff
Architecture Logic Synthesis P&R Custom
• Requires:
– Tight integration and collaboration of communications, processor
architecture, functional IP and SW infrastructure
– Tools that capture SoC Platform design intent and carries them through
implementation hierarchy from SoC architecture to transistor
The Integration SoC Platform Standard
• Requirements
– Heterogeneous integration of any IP core on any SoC at any time…to
optimize for the system software application
– Flexibility to match system application needs without over-design
– Predictable logical and physical implementation…and silicon proven
– Rapid adaptation to changing markets
– Automated derivative design and verification
• Elements
– Complete SoC communication architectures
• System level services – QoS, security, power, error management
• Flexible sockets
• Scalable fabrics
– Cycle accurate architectural performance models
– Coherent SoC capture, refinement and verification environment
SoC Solutions Address
a $60B Market Opportunity
$12B $5B $17B

Microcontrollers Value SoCs Performance SoCs
Low Complexity High Complexity
$26B
Computing and Other
Sources: Semico Research, Gartner, Inc., Electronic Trend Publications and Sonics. Data for Year 2009.
The “Virtual Corporation”
“The integration platform must
subsume the traditional design
flow, rather than displacing it”
Dr. Alberto Sangiovanni-

Vincentelli
Integrate to Collaborate
“SoC democratization “
© IPextreme, Inc. Confidential Information.
The IP Sales Problem – Window of Opportunity

constellations.ip-extreme.com

Summary
A new kind of managed sales

collaboration program for IP
companies
For more information about

Constellations – see
IPextreme people after the
lunch
Enjoy the presentations from

our Constellations members!
Constellations and
“IP that Works”
Hal Barbour
President
CAST, Inc.
DAC09 Constellations Lunch – Slide 23

CAST, Inc.
A Unique IP Provider/Developer/Partner
16 years experience
Global team of over 100 people
Engineering in USA, Czech Republic, Poland, Greece & Germany
Unique market approach

Only do digital IP, designed for reusability Sales by Region
Offer 100 cores plus system IP
Independent of semiconductor technologies and EDA tools
Both CAST-developed and partner-developed IP
Total focus on Customer Satisfaction

24/7 culture with very fast response
Always online with Email, IM, home offices
Organization almost
entirely engineers

A Broad Line of IP Products Memory & Storage
Memory Controllers
Processors Multimedia DDR1 & DDR2 SDRAM
8-bit: H.264 1080p encoder SDR mobile SDRAM
8051—fast & configurable JPEG, Speedview NAND flash
8051—small, low power Lossless JPEG SD/SDIOMMC Host
8051—entry-level JPEG-LS Storage Controllers
Z80 CPU JPEG 2000 ATA/IDE Host
16-bit: 68000, 80186XL, 387L Support Functions Device Controllers
32-bit: 68000 for AHB Video Deinterlacer Smart Card Reader,
DSP: 32025 Color Space Conv. TV & VGA Displays
Block/raster, DCT High-Res Display
Interfaces Audio Interfaces
PCI & PCI Express I2S, SPDIF System IP
USB, OTG & Hub Subsystems
Ethernet MACs Encryption 8051/USB, 8051/MAC,
FireWire AES: programmable, 8051/HDLC, MAC/PCI
CAN, LIN, I2C, SPI optimized AMBA Infrastructure
ECP DES, Triple DES Bus Interfaces,
Communications MD5 Controllers & Peripherals
IR Controllers: RC5, NEC SHA-1, SHA-256 Pre-Integrated Platforms
Synchronous UARTS Ready for ARM®,
SDLC, HDLC See more at www.cast-inc.com eASIC® & TenSilica®

Two Lessons from “IP that
Works”
Good IP …
Is not Easy
Takes a Team

Good IP is Not Easy
Preliminary
Study: Specification:
152 hours 275 hours
Test Application: 3% 6%
1041 hours RTL Coding:
21% 519 hours
11%
Test Bench
Total Hours: Coding:
422 hours
4,912 9%
Packaging:
758 hours
15%
Verification:
1,745 hours
35%
Project: USB 2.0 Device Controller Core by USB 1.1 Team

Good IP requires a Good Team
Then
Starts
Who
And
That documented
marketed
verified
supported
priced
legally
packaged
gets
needs
do
add
with
alldeveloped
all
a&
licensed
the
an
by
of
Designer
sold
so
&
IP
same
the
delivered
core
by
for
Designer
an
test
Constellations
expert
several
engineers
cancores
find
group
from
it
one vendor

CAST and IP Constellations
Good IP …
Is not Easy
Takes a Team
Constellations Partners think similarly.
Constellations Program offers the widest

variety of IP Products and best IP Team
in the industry.

Stop by CAST Booth 1421
Discuss Constellations Get scanned for
chance to win
Learn more about our your own H.264
100 cores and system encoder!
IP products
Flip Ultra HD 8 GB:
two hours 720p
Demo
new
H.264
Video
Encoder

IPextreme
Company Overview
© IPextreme, Inc.
Confidential Information.
Our Business – Unlocking Famous IP
Our Partners
Extract XPack™ IP Server
IP IP
Packaging
Picture 41
SoC Integration
Picture 50
Licensing Upload
Picture 42
Manufacturing
Support
Picture 43
Our Value - Complete IP

Internet Picture 1
2
Integration
Source Code Tests
Our Customers Download
Software & Picture 83
Drivers
IP Use
SoC Integration
EDA Neutral
Full Documentation Flow Manufacturing
© IPextreme, Inc. Confidential Information. Slide 33

Our Famous IP Partners

Famous IP Offerings
32-bit Microprocessors Debug

 Freescale Coldfire v1, v2, v4  Texas Instruments 1149.7 CJTAG
 Freescale Coldfire for Altera
 Freescale Power Architecture
 Infineon Tricore Automotive
 Freescale FlexRay
16-bit Microprocessors
 Infineon C166
 Infineon MultiCAN
 National Semiconductor CR16  Infineon Microsecond Channel
 Infineon Multiprocessor Link Interface
8-bit Microprocessor
 Mentor Graphics M8051
 Freescale HCS08
Technology Licensing
 Motorola Digital Clock Generator as
PLL replacement technology
AMBA Interfaces
 USART, I2S, I2C, AAI, CAN, Microwire,  Infineon Multicore Debug System
SmartCard,
AMBA System Functions Picture 42
 Interrupt Controller, DMA Controller,

RAM Controller, Timer & Watchdog,
Timers RTC

Industry-leading Soft Processor Cores
8-Bit Family 16-Bit Family 32-Bit Entry Level 32-Bit Mid-Range 32-Bit High-End
8-15K gates 40-90K gates 40-100K gates 100-200K gates >200K gates
ColdFire ColdFire
ColdFire ColdFire
v2
32-BITAMBA4-StgeNEXUS
v4
32-BITAMBA9-StgeNEXUS
DSP DSP
HC08 C166 Power Arch Power Arch Power Arch
HCS08 C166 v1 e200 z0 e200 z3 e200 z6

8-BIT BDM 16-BIT FPI 4-StgeOCDS 32-BITAMBA4-StgeNEXUS 32 BITAMBA4-StgeNEXUS 32 BITAMBA7-StgeNEXUS
MMU DSP VLE Only VLE MMU FPU DSP VLE MMU FPU DSP
8051 CR16 ColdFire Power Arch TriCore
M8051 CR16CP ColdFire e200 z1 TriCore1

8-BIT 2-Cyc DBG 16-BITAMBA3-StgeNEXUS v1
32-BITAMBA4-Stge BDM 32 BITAMBA4-StgeNEXUS 32 BIT FPI 4-StgeOCDS
DSP VLE MMU DSP FPU 3 Pipe

AMBA Peripheral Library
Library of 20 AMBA 2.0 Peripherals

All proven in high-volume National Semi Products
Low-cost, royalty-free
Processor
RAM (32-Bit AHB Master)
AMBA
RAM Controller DMA Controller AHB Backbone
Library
AHB System Bus
Multi-Input Real Time Timing and AMBA AHB-to-APB

Interrupt Smart Card Versatile
Wakeup Clock Watchdog Watcher Bridge
Controller Interface Timer Unit
Module Module Module
APB
Peripheral Bus
AccessBus/ Advanced General General I2S Enhanced

MICROWIRE/
I2C Full-CAN Audio Purpose Purpose I/O Audio Multi-Function
SPI Interface
Interface Interface USART Ports Interface Timer

#1 Automotive IP Portfolio
Aut om ot ive IP Lineup

Power Architecture
Picture 33
CR16
Controllers
C166
TriCore
Picture 39
FlexRay
Networking
CAN
Picture 42
Nexus5001
Debug MCDS
CJTAG 1149.7
Serial MLI
Interfaces MSC
Horizontal Peripherals

USB20Hub IP Features
Cypress USB market share leader USB HUB
Proven in Cypress EZ-USB HX2LP™ 12 Mbps LS USB

1.5 Mbps
family of Hub chips Serial
Interface
Engine
Transaction
Translator
Device
(SIE) (TT)
USB-IF and WHQL certified
USB Upstream Port

FS USB
12 Mbps
Routing Logic
Device
HS USB
Configurable: Traffic
480 Mbps HS USB
480 Mbps Device
 2-7 downstream ports Hub Repeater
 Single-TT to minimize size or 480 Mbps

HS USB
Device
 Multi-TT for max FS throughput

 Once implemented via EEPROM
Multi-TT USB HUB 12 Mbps
Supports high, full and low speed Transaction
Translator
(TT) LS USB
1.5 Mbps
Ultra-low power, runs on Bus Power Serial

Transaction
Translator
Device
Interface (TT)
Low gate count, small die size
USB Upstream Port

Engine LS USB
1.5 Mbps
Routing Logic
(SIE) Transaction Device
HS USB Translator
(TT)
Full hardware implementation, no

Traffic
Transaction FS USB
12 Mbps Device
Translator
firmware or microcode (TT)
480 Mbps
Configurable once implemented via

FS USB
12 Mbps Device
Hub Repeater
external SPI EEPROM

IEEE 1149.7 CJTAG
Industry’s First CJTAG Core

 Provides increased functionality to embedded
designs over the IEEE 1149.1 standard
 Endorsed by IEEE and MIPI standards
organizations for next generation test and debug
Supports IEEE 1149.7 classes 0–5 (selected

through hardware configuration parameter)
Partitioned along IEEE 1149.7-specified

functional boundaries (so that only the
required hardware is included):
 Extended Processing Unit (EPU) for class 0–3
operation
 Advanced Processing Unit (APU) for class 4–5
operation
 Further partitioning within EPU and APU for
class-specific and optional features Deliverables
 Separate blocks for clock and reset signal  Synthesizable source code
conditioning  Integration testbench and tests
 Documentation
Supports all mandatory and optional scan  Scripts
formats: JScan0–3, SScan0–3, OScan0–7, • Simulation and synthesis
and MScan
• Support for common EDA tools

Core Store™
What is it?
 New, hassle-free way to purchase
semiconductor IP
• No sales person involved
• No negotiation involved
• Lowest possible price
 Transparent pricing
• Standard price published on web site
• Simple (sign once) licensing contract
What’s in it?
 High value silicon-proven IP titles
suitable for a broad array of designs
• Star IP microprocessors
• AMBA peripherals
 New titles added every quarter
 Highly packaged, ready to use IP
 Support is optional
How can IPextreme do it?

 IP is very solid having been proven in
production for years at major
semiconductor companies
 IP is highly packaged so customers
can easily use the IP on their own

XPack™ IP Server
Fully Integrated IP Packaging, Distribution, Usage and Support
Consistent IP Guided EDA Secure Web Customer

Packaging Configuration Generators Distribution Support
User Area Customer Customer Administration

Support Area
Area

Constellations™ Program
Independent IP companies working

together as a community
 Open to all IP companies
 Organized by IPextreme
Connecting IP Customers to IP
Suppliers
Current Members

Company Fact Sheet
Company
 Semi IP licensing specialists
 Worldwide presence
• Corporate offices in technology centers
• Representatives in major regions
• Customers in more than 20 countries Germany Japan
 45+ titles in our portfolio Silicon Valley Israel Korea
India Taiwan
China
Technology
 Strong IP business, design, and
methodology experience
 Patent pending Xpack IP packaging,
repository, distribution, and support
system
Business
 100% focused on IP licensing
Awards
 2008 Gartner “Cool Vendor”
 2009 Red Herring “N.A.Top 100” Silicon Valley Munich Tokyo

1T-Fuse™
Embedded Non-Volatile Memory
Constellations Luncheon – DAC 2009

Who We Are
 Private company founded in 2004
 Leading embedded, field-programmable OTP
memory IP provider
 Only reliable Single-Transistor Antifuse Bit
Cell in production
 Proven technology from 180nm to 55nm and
scalable to 32nm and below
 Over 50 patents approved/pending/applied
 Support for many popular top-tier foundries
 More than 50 customer designs
46 The Future of Logic NVMTM

Embedded OTP Market Drivers
 Need for low-cost and secure digital content
 Consumer electronics (CE) devices
 Secure storage of encryption keys and boot code
 Calibration and trimming
 For A/MS circuits and sensor interfaces
 Higher silicon costs
 Increasing mask costs & shrinking times-to-market
 Need flexibility to make SW changes without re-spins
 Firmware reconfigurability by programming the OTP
with no new tape-out
Virtually every chip needs embedded OTP

with their processors, comm. cores, etc.
Target Markets for Sidense OTP
 Digital Consumer Electronics
 Mobile and Wireless
 Medical – Hearing Aids and Implantable Devices
 DSP and Microcontroller Firmware/Code Storage
 Configurable Processors and Logic
 RFID Tags
 Analog Circuits – Tuners, A/D, D/A
 LCD Panels

The Sidense Edge
 Smallest bit cell
 Broad foundry and process node support
 Configurable options – eMTP, mask ROM, High
Speed/Enhanced Security read
 Highly secure
 Most reliable bit-cell architecture

Smallest Bit Cell – 1T Split-Channel
 Patented antifuse-based bit-cell
 Programming through predictable, non-
reversible oxide breakdown
 Scalable to 32/28nm and below
WL Program Area
BL
BL
1T-Fuse™
1T-Fuse ™
LDD
N
N+
Channel ISOL
1T-Fuse is the only secure, reliable and cost-effective

antifuse-based NVM technology available

Broad Silicon Availability
 Highly scalable / very portable between
foundries
 No additional masks or process steps
 No dependence on foundry-specific “tweaks”
 Scalable to 32nm/28nm and beyond
 Broad foundry and IDM support
 Available from 180nm down to 55nm

Flexible Architecture
 ROM option
 Can design a field-programmable OTP and mask-
programmable ROM hybrid
 Flexible partitioning between OTP and ROM
 Conversion to mask ROM with one diffusion mask
 High Speed/Enhanced Security (HSS) option
 Differential Read
 Wider sensing margins
 Emulated MTP (eMTP) operation
 Small OTP bit cell  system-level MTP operation

Highly Secure
 Very difficult to reverse engineer
 One bit is programmed, the other isn’t
 Can you tell the difference?
Bit 1 Bit 2

Reliability/Qualification Tests
 Compliant to TSMC’s IP9000
 High temperature
 HTOL
 4 ½ million Mbit-hours at 125°C Accelerated High
Temperature Operating Life (AHTOL) testing with no failures
 HTS
 4 million Mbit-hours at 150°C High Temperature Storage
(HTS) testing with no failures.
 TDDB testing
 Exceeds 20 years retention at 125°C and 50% duty
cycle
 Electrostatic Discharge (ESD)
 Latchup
Summary
 Embedded NVM for standard-logic CMOS
processes
 No additional masks or process steps
 Industry leader
 Smallest cell
 Broad foundry and process node support
 Configurable options
 Highly secure
 High reliability
 Available from 180nm to 55nm at many
leading foundries

Sonics’ Success
Sonics RS CV34 1-7-08 CF-DJ Notes & Grfx Updates 1PM
• Challenge Licensees
• Sonics set out to solve the biggest problem
facing the SoC industry:
Sky-high design effort/cost.
• Proven Technology
• Sonics has succeeded in dramatically lowering
design costs by developing highly configurable
IP for the on-chip communications networks that
enable the design of complex chips.
• Key Wins with 6 of Top 10 Semi co’s
• The world’s leading companies have turned to
Sonics for their most demanding SoCs designs,
and in turn they have sold more than 500 million
chips based on Sonics’ IP.
• Technology Leader
• Sonics has invested over $65 million to develop
its unique IP:
~100 patent properties WW, 50+ US OEMs
• Market Leader
• Sonics is the Number 1 global provider of on-
chip communications network IP.
56
SoC Design Challenges: 32nm and Beyond
Our customer base sees the following SoC challenges:
• Complexity measures
• 100’s of millions of gates!
• 10’s-100’s of power gated domains
• 10’s of voltage domains
• Distributed, heterogeneous architectures
• Microprocessors, heterogeneous computing engines everywhere
• Memory hierarchy (on-chip, die2die, off-chip) with
increasing hunger for memory BW
• Virtual memory, message passing, cache coherence
• Dynamic resource management – HW & SW
• Task scheduling
• Memory allocation & migration
• Power optimization
• Security, QoS, Errors, etc.
• More hierarchy – subsystems of subsystems
57
From the beginning . .
. . SoC Communications Network Solutions
Architecture Products Network Fabric Agents IP I/F
Protocols
XBar Fabric
SonicsSX™
le
ab
Socket I/F
Regs
Decoupling
SM
SM
er
SonicsMX™ Buffer
OCP
op
Fabric I/F
r
Gen 3: and/or
te
SonicsLX™ • DRAM
Increasing SoC Complexity
Dolphin APB
In
Channel
Increasing Capabilities
Shared Bus Fabric Load
d
Stingray Balancing
an
AHB
• 2D addressing
le
SNAP™
tib • Security
• Error handling AXI
pa
Shared Bus Fabric • QoS

m
Gen 2: Sonics3220™ • IP bus I/F Proprietary

Co
TigerShark abstraction
Shared Bus Fabric

Gen 1: Silicon
Backplane™
Sonics IA
Studio™
Additional Sonics products: MemMax™, Sonics Express™
58
Multicore Mobile Handset Example
P P P P P P P
P P P P P
T T T T T T T T T T T T
T
S3220 T T T T T
P T T P
MP3
USB 2.0
CPU Tile 2D/3D Graphics MPEG4 Codec P P
Tile Tile
P T Partial XBar P T
T P
Fabric Agent
Simple
P T Socket Shared Bus Fabric
Socket I/F
T P
Regs
Decoupling
SM
SM
Buffer
16
Fabric I/F
P T T P
Flash Controller
I I I I I
SSX/SMX
I T SSX/SMX T I
T P
I T I I I I I
T
T T
MMU
Controller
X Inst.
Interface
Camera
Embedded DMA T P
RAM Cache
LCD
SRAM
DMA
Complex MemMax
Memory P P P T P
Socket Scheduler Data Y DSP T T T T T T
Cache RAM Core T
128 T T T T T T
DRAM
Controller DSP Tile P P P P P P 59
SoC Development Flow
Sonics
SoC Creator GUI
generate
generate
configure
SystemC Simulation SoC Generation RTL
• Analyze Performance • Verification
• Throughput • Cost Analysis
• Latency • Area
• Configure interconnect • Power
• Configure memory controller • Timing Closure
60
SMART Interconnect Approach
Addresses the Global Interconnect Challenge
Virtual Prototyping Perf. Verification
Parallel IP Creation
Arch. Modeling
Design Re-use
SW Development Methodology
& Automation Variable Clock Freq.
Timing Closure
Voltage Isolation
Complex Memory
Power Management
Hierarchies
Intelligen
Scalable
t Error Management
Signal Integrity Fabrics
Agents
Access Security
High Peripheral Count
Data Width Conversion
Distributed Processing
Mixed Endianness
Guaranteed BW QoS Pipelining Protocol Conversion
61
Blue Chip Customers Choose Sonics
Strategic Drivers
• Faster SoC Design Completions with

Fewer People
• Lower Risk for Schedule and Features
• Leverages Economy of Sonics’ Scale
• Delivers Innovative System-level
Features
• Multiplies Effectiveness of Key System
Architects
• Enables Focus on Differentiating
Technology
Sonics Solutions
• Best Power, Performance and Area

• Fastest Design Cycle
• Lowest Design Cost
62

Constellations DAC09 Presentation

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SoC Democratization

Jim Hogan - DAC 2009

“We don’t want our engineers writing Verilog,

Yoshihito Kondo – General Manager

The ideal collaboration model is the VIRTUAL

Chip design has moved from

ARM MPEG • Teams spread across 3 continents

[Source: Texas Instruments]

INFINEON LINEAR TECH NXP NUMONYX

Source: Dr. Alberto Sangiovanni-Vincentelli

INFINEON LINEAR TECH NXP NUMONYX

Source: Dr. Alberto Sangiovanni-Vincentelli

Source: Dr. Alberto Sangiovanni-Vincentelli

Architecture SoC Platform signoff

RTL/Logic Functional signoff

Synthesis Netlist Timing signoff

Custom Foundry Transistor Model

. Source: Dr. Alberto Sangiovanni-Vincentelli

Architecture Logic Synthesis P&R Custom

$12B $5B $17B

Low Complexity High Complexity

Dr. Alberto Sangiovanni-

© IPextreme, Inc. Confidential Information.

© IPextreme, Inc. Confidential Information.

A new kind of managed sales

For more information about

Enjoy the presentations from

DAC09 Constellations Lunch – Slide 23

Unique market approach

Total focus on Customer Satisfaction

DAC09 Constellations Lunch – Slide 24

DAC09 Constellations Lunch – Slide 25

DAC09 Constellations Lunch – Slide 27

Project: USB 2.0 Device Controller Core by USB 1.1 Team

DAC09 Constellations Lunch – Slide 28

DAC09 Constellations Lunch – Slide 29

Constellations Partners think similarly.

Constellations Program offers the widest

DAC09 Constellations Lunch – Slide 30

DAC09 Constellations Lunch – Slide 31

Our Value - Complete IP

© IPextreme, Inc. Confidential Information. Slide 33

© IPextreme, Inc. Confidential Information. Slide 34

32-bit Microprocessors Debug

AMBA System Functions Picture 42

 Interrupt Controller, DMA Controller,

© IPextreme, Inc. Confidential Information. Slide 35

HC08 C166 Power Arch Power Arch Power Arch

HCS08 C166 v1 e200 z0 e200 z3 e200 z6

8051 CR16 ColdFire Power Arch TriCore

M8051 CR16CP ColdFire e200 z1 TriCore1

© IPextreme, Inc. Confidential Information. Slide 36

Library of 20 AMBA 2.0 Peripherals

Multi-Input Real Time Timing and AMBA AHB-to-APB

AccessBus/ Advanced General General I2S Enhanced

© IPextreme, Inc. Confidential Information. Slide 37

Aut om ot ive IP Lineup

© IPextreme, Inc. Confidential Information. Slide 38

Proven in Cypress EZ-USB HX2LP™ 12 Mbps LS USB

USB-IF and WHQL certified

USB Upstream Port

 2-7 downstream ports Hub Repeater

 Single-TT to minimize size or 480 Mbps