Analog Integrated Circuits

Lecture 1: Introduction and MOS

Physics
ELC 601 Fall 2013

Dr. Ahmed Nader
Dr. Mohamed M. Aboudina
anader@ieee.org
maboudina@gmail.com

Department of Electronics and Communications Engineering
Faculty of Engineering Cairo University
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Syllabus
Text book:
Design of Analog CMOS Integrated Circuits by Behzad Razavi
Website: http://scholar.cu.edu.eg/anader/
Email: anader@ieee.org
Office hours:
Sunday 4:00 5:00 pm
Monday 4:00 5:00 pm
Week Lecture/Studio Topic Chapter
1 MOS Physics + Short Channel Effects 2 + 16
2 Single Stage Amplifiers + Frequency Response 3 + 6
3 Differential Amplifiers 4
4 Current Sources/Mirrors 5
5 Operational Amplifier Design 9
6 Operational Amplifier Design 10
7 Operational Amplifier Design 10
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Contents
Analog Signal Processing Vs. Digital Signal Processing
IC Fabrication
Passives
MOS: Device Physics
MOS Structure and Threshold Voltage
MOS I-V Characteristics
MOS Non-idealities (Channel length modulation, Body effect)
Subthreshold Conduction
MOS Intrinsic capacitance and small-signal model
Velocity Saturation




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Digital Signal Processing
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Analog Signal Processing
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Analog Signal Processing
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Data Converters
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Integrated Circuits
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IC Fabrication
Semiconductor device fabrication is the process used to
create integrated circuits (silicon chips)
Done in a clean room (Fab facility)
Takes 6-8 weeks
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Video
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Semiconductor Industry
Semiconductor IC industry had revenues that reached $295
billion last year (2012).
Microcontrollers (MC), Digital Signal Processors (DSP) and
Microprocessors (MP) have been the center of the IC revolution
since the beginning.
The Personal Computer (PC) boom of the last century has
become the Smartphone, Entertainment Console, Notebook
and Tablet explosion in the new millennium.
Largest companies in that industry are: Intel with $50 billion
revenue in 2012. Samsung Electronics ranked second.
Qualcomm, Texas instruments, Toshiba rounding out the top 5.
Largest manufacturers (Fab facilities): Intel, TSMC,
STMicroelectronics, IBM
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CMOS Cross Section
PDK=Process Development Kit
Remember Z dimensions cannot be changed and are fab dependent
14
Devices in a PDK
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Integrated Resistors
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Integrated Resistors
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Diffusion Resistors
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Integrated Capacitors: Poly-Poly
In range of pF
Accuracy +/-15%
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Integrated Capacitors: MIM (Metal-Insulator-Metal)
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Integrated Capacitors: MOM (Metal-Oxide-Metal)
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Integrated Inductors
Widely Used in RF circuits (L in the range of nH)
Low quality factor
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Integrated Inductors: Multi-Layer Spiral Inductors
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An Example of a Commercial IBM Process
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An Example of a Commercial IBM Process
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Packaged Chip + Chip Micrograph
Wi-Fi Receiver
17mm
2
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MOS Structure
A piece of polysilicon with a width of W and length of L on top of a
thin layer of oxide defines the gate area.
Source and drain areas are heavily doped.
Substrate usually tied to the most negative voltage.
Leff = L 2L
D
, where L
D
is the side diffusion of source and drain.
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MOS characteristics Threshold Voltage

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MOS characteristics Threshold Voltage
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MOS characteristics Threshold Voltage
Remember PVT (Process, Voltage, Temperature Variations)
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MOS I-V characteristics
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MOS I-V characteristics
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MOS I-V characteristics
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MOS Device as a Resistor
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MOS I-V characteristics
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MOS I-V characteristics
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MOS: In Saturation
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MOS: Channel length modulation
Channel length modulation by V
DS

causes the saturation current to
vary with V
DS
.

is the channel length modulation parameter (V
-1
)
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MOS: Channel length modulation
undesired second order effect
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MOS: Substrate or Body Effect
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MOS: Bulk Driven
Can be used in low-voltage applications
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Body Effect: Non-linearity
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Substrate: Where to connect it?
For NMOS
To the most negative available potential
To a carefully designed potential (for example source such that V
SB
=0)
in the case of twin well process or triple well (deep NWELL) process
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Triple Well Option
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Region of Operation: Conceptual Visualization
V
DS
< V
GS
-V
TH
MOS transistor in linear region.
In linear region, MOS transistor acts as a resistor or a switch.
NMOS PMOS
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MOS: Subthreshold (Weak Inversion)
Subthreshold Conduction:
For V
GS
near V
TH
, I
D
has an exponential dependence on V
GS
:
Max transconductance efficiency
Used for low currents & low frequency applications












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MOS: Intrinsic Capacitance
C1 is the gate-channel capacitance
C2 is the channel-bulk depletion capacitance
C3 & C4 is the overlap gate-source(drain) capacitance
C5 & C6 is the source/drain bulk junction capacitance (bottom-
plate and sidewall)
Note that junction capacitors are voltage-dependent (non-linear)
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MOS: Intrinsic Capacitance
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MOS Device as a Capacitor: Varactor
Assignment 1a:
There is a special device with n-doping in
an NWELL. Plot the characteristics of such
a device. Comment on its properties.
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Small Signal Model
The slope of the diode characteristic at the
Q-point is called the diode conductance
and is given by:





g
d
is small but non-zero for I
D
= 0 because
slope of diode equation is nonzero at the
origin.
Diode resistance is given by:


g
d
=
ci
D
cv
D
Q point
=
I
S
V
T
exp
V
D
V
T
|
\


|
.
|
|
=
I
D
+I
S
V
T
g
d
~
I
D
V
T
~
I
D
0.025V
=40I
D
for I
D
>>I
S

r
d
=
1
g
d
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Small Signal Operation of a Diode

i
D
=I
S
exp
v
D
V
T
|
\


|
.
|
|
1






(

(
(
(
(
I
D
+i
d
=I
S
exp
V
D
+v
d
V
T
|
\


|
.
|
|
1






(

(
(
(
(
I
D
+i
d
=I
S
exp
V
D
V
T
|
\


|
.
|
|
1






(

(
(
(
(
+I
S
exp
v
D
V
T
|
\


|
.
|
|
v
d
V
T
+
1
2
v
d
V
T
|
\


|
.
|
|
2
+
1
6
v
d
V
T
|
\


|
.
|
|
3
+...





(

(
(
(
Subtracting I
D
from both sides of the equation,

i
d
=(I
D
+I
S
)
v
d
V
T
+
1
2
v
d
V
T
|
\


|
.
|
|
2
+
1
6
v
d
V
T
|
\


|
.
|
|
3
+...





(

(
(
(
For i
d
to be a linear function of signal voltage v
d
,
This represents the requirement for small-signal operation of the diode.
mV v V v
d T d
5 or V 05 . 0 2 s = <<

i
d
=(I
D
+I
S
)
v
d
V
T
|
\


|
.
|
|
=g
d
v
d
i
D
=I
D
+g
d
v
d
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Current Controlled Attenuator
Magnitude of ac voltage v
o
developed
across diode can be controlled by value
of dc bias current applied to diode.
From dc equivalent circuit I
D
= I,
From ac equivalent circuit,

v
o
=v
i
r
d
r
d
+R
I
|
\


|
.
|
|
=v
i
1
1+
R
I
r
d
v
o
=v
i
1
1+
(I +I
S
)R
I
V
T
For R
I
= 1 kO, I
S
= 10
-15
A,
If I = 0, v
o
= v
i
, magnitude of v
i
is
limited to only 5 mV.
If I = 100 A, input signal is
attenuated by a factor of 5, and v
i

can have a magnitude of 25 mV.
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Small-Signal Model of a MOS (Two-Port Model)
Using 2-port y-parameter network,


The port variables can represent either
time-varying part of total voltages and
currents or small changes in them away
from Q-point values.

i
g
= y
11
v
gs
+y
12
v
ds
i
d
= y
21
v
gs
+y
22
v
ds

y
11
=
i
g
v
gs
v
ds
= 0
=
ci
G
cv
GS
Q point
=0
y
12
=
i
g
v
ds
v
gs
= 0
=
ci
G
cv
DS
Q point
=0
y
21
=
i
d
v
gs
v
ds
= 0
=
ci
D
cv
GS
Q point
=
2I
D
V
GS
V
TN
y
22
=
i
d
v
ds
v
gs
= 0
=
ci
D
cv
DS
Q point
=
I
D
1

+V
DS
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Small-Signal Model of a MOS
Since gate is insulated from
channel by gate-oxide input
resistance of transistor is infinite.
Small-signal parameters are
controlled by the Q-point.
For same operating point, MOSFET
has lower transconductance and
lower output resistance that BJT.
Transconductance:

g
m
= y
21
=
2I
D
V
GS
V
TN
= 2K
n
I
D
Output resistance:
D
o
I y
r

1 1
22
~ =
MOS Transistor
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MOS Transistor
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Small Signal Model: Body Effect
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Drain current depends on threshold voltage which in
turn depends on v
SB
. Back-gate transconductance
is:










0 < q < 1 is called back-gate tranconductance
parameter.


g
mb
=
ci
D
cv
BS
Q point
=
ci
D
cv
SB
Q point
g
mb
=
ci
D
cV
TN
|
\


|
.
|
|
cV
TN
cv
SB
|
\


|
.
|
|
Q point
=(g
m
q)=g
m
q
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Small-Signal Model of a MOS: High Frequency Model
Voltage dependent current source (g
m
V
gs
) models dependence of
drain current on gate-source voltage
Output resistance models dependence of drain current on drain-
source voltage (channel length modulation)
Voltage dependent current source (g
mb
V
bs
) models dependence of
drain current on bulk-source voltage (body effect)



MOS Transistor
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Useful Model
Small Signal:
+
-
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MOS Transistor
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Special Cases
Bias point
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Deep Sub-Micron Technologies
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Low-voltage High-
Speed trade-off
Fixed for the
technology and
fixed L
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Deep Sub-Micron Technologies
Some small geometry effects:
1- Gate leakage
2- Threshold voltage variation
3- Output impedance variation with V
DS
(non-linearity
)


4- Mobility degradation with vertical field
5- Velocity saturation
6- Reliability Effects (GO, Hot Carrier, NBTI, ..)
7- Stress Effects (STI, Well Proximity, ..)

Assignment 1b:
Choose one of those effects and describe it in details
(physical meaning, effect on performance, etc.)
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Deep Sub-Micron Technologies
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What about scaling of V
th
?
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Deep Sub-Micron Technologies Mobility degradation with Vertical Field
Carriers are confined to a narrower region below oxide-
silicon interface leading to more carrier scattering and hence
lower mobility

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Deep Sub-Micron Technologies Velocity Saturation
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Deep Sub-Micron Technologies Velocity Saturation
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MOS Device Models
Level 3 Model
BSIM (Berkeley Short-Channel IGFET Model)