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Combinatorial components: the output values are computed only from their present input values. Sequential components: their output values are computed using both the present and past input values. Sequential circuits can contain only a finite number of states finite state machines Synchronous and Asynchronous
Sequential Circuits
Contains Memory Elements Asynchronous sequential circuits change their state and output values when input changes Synchronous sequential circuits change their output values at fixed points of time, which are specified by the rising or falling edge of a clock signal Clock period is the time between successive transitions in the same direction Active high state changes occur at the clocks rising edge( on higher voltage) Active low state changes occur at the clocks falling edge( on lower voltage)
Gated D-Latch
Ensures S and R inputs never equal to 1 at the same time Useful in control application where setting or resetting a flag to some condition is needed Stores bits of information Constructed from a gated SR latch and a Data latch
D Flip-Flop
D Q+ 0 0 1 1
Characteristics : Q+ = Next State
Synchronous Avoids the instability of RS flip-flop Retains its last input value To set the ff, place 1 on D input and pause the CK input To reset, place 1 on D input and pause the CK input
JK Flip Flop
J Set K Reset
T Flip-Flop
T D
SET
CLR
T 0 1
T = 1 force the state change T = 0 state remain the same
Q+ Q Q
D and JK Flip-Flop
D
SET
CLR
D 0 1 J 0 0 1 1 K 0 1 0 1
Q+ 0 1 Q+ Q 0 1 Q
SET
CLR
Q+
0 1
J 0 0 1 1
K 0 1 0 1
Q+ Q 0 1 Q
D ffs property: When in = 0, the out(Q+) = 0. When in = 1, the out(Q+) is 1 invert K invert K
SET
CLR
State change
SET
T
K
CLR
KQ J
0 1
Q+ 0 1
D = JQ + KQ
J
D
SET
K
CLR
KQ 00
J 0 1 0 1
01
0 0
11
1 1
10
0 1
Q+ Q Q
T = KQ + JQ
T D
SET
CLR
D 0 1
Q+ 0 1
T0
0 1 0 1 1 0
T 0 1
Q+ Q Q
D = TQ + TQ
SET
CLR
Q+ 0
D 0 1 0 1
1
1 0
T = DQ + DQ
T D
SET
D
CLR
SR-Flip Flop
S R Q Q
0 1 0 1
S 1 0 1 0
0 0 1 1
R 1 1 0 0
Q 1 0 0
Q Q 1 0 1
Q 0 1 0
Q Q 0 1 1
SET RESET
SET RESET
SR-Flip Flop
Asynchronous If S=0 and R=1, Q is set to 1, and Q is reset to 0 IF R=0 and S=1, Q is reset to 0, and Q is set to 1 If S=1 and R=1, Q and Q maintain their previous state If S=0 and R=0, a transition to S=1, R=1 will cause oscillation
SET
CLR
Clocked SR Flip-Flop
Similar to SR Flip-flop but with extra control input C, which enables or disables the operation of S and R inputs.
SET
CLR
Instability
RS flip-flops can become unstable if both R and S are set to 0 All sequential elements are fundamentally unstable under certain conditions
Invalid transitions Transitions too close together Transitions at the wrong time
Positive-edge-triggered D Flip-Flop
When CLK=0 the master latch is open and the content of D is transferred to QM When CLK=1 the master is closed and its output is transferred to the slave Master and slave latches are never enabled at the same time
References
www.play-hookey.com/digital www.infopad.eecs.berkeley.edu/~icdesign/ SLIDES/slides6.pdf www.cs.mun.ca/~paul/cs3724/material/we b/notes/node14.html Dos Reis, Assembly Language and Computer Architecture Using C++ and Java