Programmable Logic Devices

Indresh Kumar Verma Asst. Prof. Deptt. of Electronic & Instrumetation

Introduction :
Programmable Logic Devices (PLDs) refer to integrated ckt which can be programmed to implement any design. PLDs were introduced in 1970s , with an idea to design a single purpose chip which can be programmed to meet particular hardware requirement. PLDs are a genereal purpose chip for implementing logic circuitry. It consist of logic circuit elements that can be coustamized in different ways. The first PLDs were called PAL (Programmable Array Logic) or PLA (Programmable Logic Array), depending on the programming scheme. They used only logic gates (no flip-flops), thus allowing only the implementation of combinational circuits. Registered PLDs were launched to overcome this problem, which included one flip-flop at each output of the circuit. With them, simple sequential functions could then be implemented as well.

Types of PLDs
Broadly classified in folowing categories
SPLD (Simple PLDs) CPLD (complex PLDs)

PLDs
SPLDs CPLDs

SPLDs are simple PLDs which can handle up to 10 - 20 logic equations only & ment for simple design.
A typical SPLD is a two level array of logic gates AND - OR with programmable switches and gives output in SOP form. SPLDs are of 4 types :

PLAs PALs Registered PLAs GALs

FPGAs

PLAs (Programmable Logic Arrays)

PLAs are SPLD. introduced in 1970s. It has two level of logic implementation wired AND plane & wired OR plane. Both AND & OR Planes are programmable.

x1 x2

Input Buffer & Inverters

f1 f2
Programmable

Programmable

AND
Plane

OR
Plane

xn The basic Structure of PLA

fn

Internal structure of PLA

 The output of PLA is in SOP form.

Two level of programmability gave flexibility to design any logic circuit. It led to low speed.
Making Both AND - OR configrable made the manufacturing cost very high. This led to introduction of PALs.

PALs (Programmable Array Logic)

PAL are PLDs with only AND plane Programmable & OR plane fixed. Output in SOP form. The ouptut of OR gate are connected to F/F so as to realize sequential circuits.
x1 x2 F/F Input Buffer & Inverters
Programmable Fixed

AND
Plane

OR
Plane

xn

F/F

Basic Structure of PAL / Registered PALs.

Implementation of Logic function using PAL

(2,4,6,7) ( A, B, C )

Advantage of PLDs
The biggest advantage of a PLD is its programmability. A PLD is not a one time device. It can be programmed again & again. To reprogram a PLD, it is not required to be removed from the PCB but can be programmed on the field, due to this reason PLDs are also known as FPLDs (Field PLDs). A PLD could handle large, complex design. It could be easily implemented with single PLD in comparision to the previously used SSI & MSI Circuits, with comming of CPLD & FPGA the capacity to handel complexity has increased. Due to use of single chip for circuit implementation, the cost of design impementation decreased drastically.

Difference between FPGA & CPLD

FPGA
FPGA consist of configurable logic blocks, I/O blocks interconnected by routing channels. They donot contain AND-OR planes. They are much more versatile than CPLDs with much higher logic capacity & hence used for complex level design. They generally use SRAM technology for programmable switches.

CPLD
It is a conection of PAL like structure interconnected by programable switch matrix. AND-OR plane form the backbone of CPLD structure. It is limited to moderate level of design complexity.

They rely on E2PROM/flash technology for programming interconnects.

Logic capacity of FPGA is much higher Logic capacity is lower than FPGAs than CPLDs.