CHAPTER 6

Combinational Circuit Building Blocks

Chapter Objectives

In this chapter you will learn about:

Commonly

used combinational subcircuits Multiplexers, which can be used for selection of signals and for implementation of general logic functions Circuits used for encoding, decoding, and codeconversion purposes Key VHDL constructs used to define combinational circuits

A 2-to-1 Multiplexer
s w0 w1
0

(a) Graphical symbol

w0

s
s 0 1 f w0 w1 w1

(b) Functional table

(c) Sum-of-products circuit

A 4-to-1 Multiplexer
s0 s1 w0 w1 w2 w3
00 01 10 11

s0
f w0

s1
w1 f

(a) Graphic symbol

s1 s0
0 0 1 1 0 1 0 1

f
w0 w1 w2 w3

w2

w3

(b) Functional table

(c) Circuit

F = s1 s0 w0+ s1 s0 w1 + s1 s0 w2 + s1 s0 w3

Using 2-to-1 Multiplexers to Build a 4-to-1 Multiplexer

s1 s0 w0 w1

0 1 0 1

w2 w3

0
1

A 16-to-1 Multiplexer

A Practical Application of Multiplexers

x1

0 1

y1

x1 x2

y1 y2 x2

s
0 1

y2

(a) A 2x2 crossbar switch (b) Implementation using multiplexers

Synthesis of a Logic Function Using Multiplexers

w1 w2 0 w1 w2 f 0 1 1 0 0 1 1 0 f w2 w1 0 1 1 0 1 0 1 f 0 1 1 0 w1 0 1

f
w2 w2

0 0
1 1

0 1
0 1

(b) Modified Table, a Functional table w1

(a) Implementation using a 4-to-1 multiplexer

w2 f

(c) Circuit

Implementation of the Three-Input Majority Function Using a 4-to-1 Multiplexer

w1 w2 w3

w1 w2

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

0 0 1 1

0 1 0 1

0
w3 w3 w3

w2 w1

0 1

(c) Circuit

(a) Truth table

(b) Modified Functional table

Three-Input XOR Implemented with 2-to-1 Multiplexers

w1 w2 w3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

f 0 1 1 0 1 0 0 1

w2 w3 w3

w2

w1 f

w2 w3

(a) Truth table

XOR implementation using Fig 6.7. (b) Circuit

Three-Input XOR Function Implemented with a 4-to-1 Multiplexer

w1 w2 w3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 f 0 1 1 0 1 0 0 1 w3 w2 w1 w3 f

w3
w3 w3

(a)Truth table

(b) Circuit

The Three-Input Majority Function Implemented Using a 2-to-1 Multiplexer

w1 w2 w3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

f 0 0 0 1 0 1 1 1 (a) Truth table (b) Circuit w1 f w2w3 w2 + w3 w2 w3 w1 f

0 1

Comparison of Three-Input XOR Implementations using 2-to-1 and 4-to-1 Multiplexers

w2 w3

w1
f

w2 w1
w3 f (b) Circuit

XOR implementation using Fig 6.7.

(a) Circuit

Truth Tables for Comparison of Three-Input XOR Implementations using 2-to-1 and 4-to-1 Multiplexers

w1 w2 w3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

f 0 1 1 0 1 0 0 1

w1 w2 w3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

f 0 1 1 0 1 0 0 1 w3 w3 w3 w3

w2 w3

w2 w3

(a) Functional table

(b) Functional table

An Example

Implement the function f = w1 w2+ w1w3 + w2 w3 using only:

4-to-1 Multiplexers 2-to-1 Multiplexers

4-to-1 Multiplexer Implementation

w1 w2 w3

w1 w2

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

0 0 1 1

0 1 0 1

0
w3 w3 w3

w2 w1

0 1

(c) Circuit (b) Modified Functional table

(a) Truth table

2-to-1 Multiplexer Implementation

Hint: Expand 4-to-1 Multiplexers Using 2-to-1 Multiplexers

w2

w1

0 w3
f

(d) Circuit

An n-to-2n Binary Decoder

w0 n inputs wn 1 Enable En

y0
2n outputs

y2n 1

A 2-to-4 Decoder
En w1 w0 1 1 1 1 0 0 0 1 1 x 0 1 0 1 x y0 y1 y2 y3 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 w0 y0 w1 y1 (a) Truth table y2 w0 w1 En y0 y1 y2 y3

y3

En (c) Logic circuit

(b) Graphical symbol

A 3-to-8 Decoder Using Two 2-to-4 Decoders

w0 w1 w2 w0 w1 En y0 y1 y2 y3 y0 y1 y2 y3

En

w0 w1 En

y0 y1 y2 y3

y4 y5 y6 y7

A 4-to-16 Decoder Built Using a Decoder Tree

A 4-to-1 Multiplexer Built Using a Decoder

w0

w1 s0 s1 1

w0 w1
En

y0 y1 y2 y3

f w2

w3

A 2n-to-n Binary Encoder

w0
2n inputs w2n 1

outputs y0 n yn 1

A 4-to-2 Binary Encoder

w3 w2 w1 w0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0

y1 y0 0 0 1 1 0 1 0 1

w0 w1 w2 w3 y1

y0

(a) Truth table

(b) Circuit

Truth Table for a 4-to-2 Priority Encoder

w3 w2 w1 w0 0 0 0 0 1 0 0 0 1 x 0 0 1 x x 0 1 x x x

y1 y0 d 0 0 1 1 d 0 1 0 1

z 0 1 1 1 1

A BCD-to-7 Segment Display Code Converter

w0 w1 w2 w3 a b c d e f g

w3 w2 w1 w0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1

a 1 0 1 1 0 1 1 1 1 1

b 1 1 1 1 1 0 0 1 1 1

c 1 1 0 1 1 1 1 1 1 1

d 1 0 1 1 0 1 1 0 1 1

e 1 0 1 0 0 0 1 0 1 0

f 1 0 0 0 1 1 1 0 1 1

g 0 0 1 1 1 1 1 0 1 1

(a) Code converter a f e g d b c

(c) Truth table

(b) 7-segment display

A Four-Bit Comparator Circuit

Truth Table for an 8-to-3 Binary Encoder

Circuit for Example 6.27

Binary to Gray Code Conversion

VHDL Code for a 2-to-1 Multiplexer

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s f END mux2to1 ;

: IN : OUT

STD_LOGIC ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF mux2to1 IS BEGIN WITH s SELECT f <= w0 WHEN '0', w1 WHEN OTHERS ; END Behavior ;

VHDL Code for a 4-to-1 Multiplexer

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 s f END mux4to1 ;

: IN : IN : OUT

STD_LOGIC ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ;

VHDL Code for a 4-to-1 Multiplexer

LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE mux4to1_package IS COMPONENT mux4to1 PORT ( w0, w1, w2, w3 s f END COMPONENT ; END mux4to1_package ;

: IN : IN : OUT

STD_LOGIC ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ;

Hierarchical Code for a 16-to-1 Multiplexer

1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY work ; USE work.mux4to1_package.all ; ENTITY mux16to1 IS PORT ( w s f END mux16to1 ;

: IN : IN : OUT

STD_LOGIC_VECTOR(0 TO 15) ; STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Structure OF mux16to1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

VHDL Code for a 2-to-4 Binary Decoder

Specification of a 2-to-1 Multiplexer Using a Conditional Signal Assignment

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END Behavior ;

VHDL Code for a Priority Encoder

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT ( w : IN y : OUT z : OUT END priority ;

STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF priority IS BEGIN y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ;

Less Efficient Code for a Priority Encoder

VHDL Code for a Four-Bit Comparator

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN AeqB, AgtB, AltB : OUT END compare ;

STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ;

VHDL Code for a Four-Bit Comparator for Signed Numbers

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ;

ENTITY compare IS PORT ( A, B AeqB, AgtB, AltB END compare ;

: IN : OUT

SIGNED(3 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ;

Code for a 16-to-1 Multiplexer Using a Generate Statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.mux4to1_package.all ; ENTITY mux16to1 IS PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux16to1 ; ARCHITECTURE Structure OF mux16to1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Muxes: mux4to1 PORT MAP ( w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

Hierarchical Code for a 4-to-16 Binary Encoder

A 2-to-1 Multiplexer Specified Using an IfThen-Else Statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN IF s = '0' THEN f <= w0 ; ELSE f <= w1 ; END IF ; END PROCESS ; END Behavior ;

Alternative Code for a 2-to-1 Multiplexer Using an If-Then-Else Statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY mux2to1 IS PORT ( w0, w1, s f END mux2to1 ;

: IN : OUT

STD_LOGIC ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN f <= w0 ; IF s = '1' THEN f <= w1 ; END IF ; END PROCESS ; END Behavior ;