Combinational circuits

Comparator

To test the equality of two numbers the following circuit can be used (two 4 bit numbers):
a 0 0 1 1 b z 0 1 1 0 0 0 1 1
a0 b0 a1 b1 a2 b2 a3 b3

XNOR

Comparator (continued)

The above circuit is very straightforward to understand considering what an XNOR gate does. The following circuit tests the inequality a>b, by first testing to see whether a3 is 1 and b3 is 0 and doing the same test for lower bits if these bits are equal.
a0 b0

a1 b1

a2 b2

a3 b3

Comparator (continued)

The 7485 is a standard comparator package with the following attributes: if (A>B) lt=0, eq=0, gt=1 if (A<B) lt=1, eq=0, gt=0 4 A if (A=B) lt=l, eq=e, gt=g B
4 l e g lt eq gt

Quote: The three l, e and g inputs are used when cascading.

Comparator (continued)

Let us now cascade four of the 7485 to construct a 16 bit comparator.

a[ 15:0 ] b[ 15:0 ]
[15:12] [15:12] [11:8] [11:8] [7:4] [7:4] [3:0] [3:0]

4 A 4 B l e g

4 lt eq gt 4

A B l e g

4 lt eq gt 4

A B l e g

4 lt eq gt 4 0 1 0

A B l e g

lt eq gt

gt eq lt Final results of comparison

Comparator (continued)

This comparator will first compare the 4 most significant bits of the two inputs, unless they are equal the result can be found in this first stage as a is less than b if its 4 MSB are smaller and is greater if the 4 MSB are larger. If these 4 MSB of the two numbers turn out to be equal, the comparator will recursively do the same comparison on less significant bits four by four.

Comparator (continued)

The comparators we have seen so far have been magnitude comparators, that is they only work correctly when their inputs are unsigned numbers. To be able to use the same comparators for 2s complement numbers, some glue logic needs to be used which is:
a3 b3 gt 0 1 1 0 1 3 00 0 2 1 7 01 1 6 1 5 sgt 11 0 4 0 10 0

a3 b3 lt 0 1 1 0

00 0 2 1 3

01 0 6 0 7

11 0 4 1 5

10 1

1 slt

sgt a 3.b3 a 3.gt b3.gt

slt a 3.b3 lt.a 3 lt.b3

Comparator (continued)

Lets design a maximum finder using a comparator and a MUX:

a b 4 4 0 1 0 l e g 4 4 A B lt eq gt

0 1

Max(a,b)

Gate-level (SSI) Design: Half Adder

Design procedure:
1) State Problem
Example: Build a Half Adder to add two bits

2) Determine and label the inputs & outputs of circuit.

Example: Two inputs and two outputs labelled, as follows:
X Y S C
X 0 0 1 1 Y 0 1 0 1 C 0 0 0 1 S 0 1 1 0

Half Adder
(X + Y)

3) Draw truth table.

Gate-level (SSI) Design: Half Adder

4) Obtain simplified Boolean function.
Example: C = XY S = X'Y + XY' = XY
X 0 0 1 1 Y 0 1 0 1 C 0 0 0 1 S 0 1 1 0

5) Draw logic diagram.

X Y
S

Half Adder
C

Gate-level (SSI) Design: Full Adder

Half-adder adds up only two bits. To add two binary numbers, we need to add 3 bits
(including the carry).

Example:
+

0 0 1

0 1 0

1 1 1

1 1 0

carry X Y S

Need Full Adder (so called as it can be made from two halfadders).
X Y Z

Full Adder
(X + Y + Z)

S
C

Gate-level (SSI) Design: Full Adder

Truth table:
X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 C 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1

Note: Z - carry in (to the current position) C - carry out (to the next position)
YZ
X

C
00 01 11 1 10

0 1
YZ
X

Using K-map, simplified SOP form:

C = XY + XZ + YZ S = X'Y'Z + X'YZ'+XY'Z'+XYZ

S
00 01 11 1 1 1 10 1

0 1

Gate-level (SSI) Design: Full Adder

Alternative formulae using algebraic manipulation:
C = XY + XZ + YZ = XY + (X + Y)Z = XY + ((XY) + XY)Z = XY + (XY)Z + XYZ = XY + (XY)Z S = X'Y'Z + X'YZ' + XY'Z' + XYZ = X'(Y'Z + YZ') + X(Y'Z' + YZ) = X'(YZ) + X(YZ)' = X(YZ) or (XY)Z

Gate-level (SSI) Design: Full Adder

Circuit for above formulae:
C = XY + (XY)Z S = (XY)Z
X Y
(XY)

S
(XY)

C Z

Full Adder made from two Half-Adders (+ OR gate).

Gate-level (SSI) Design: Full Adder

Circuit for above formulae:
C = XY + (XY)Z S = (XY)Z
X Y
X Y Sum
(XY)

Block diagrams.

Half Adder
Carry
(XY)

X Y

Sum

Half Adder
Carry

Full Adder made from two Half-Adders (+ OR gate).

Code Converters
Code converters take an input code, translate to its
equivalent output code.
Input code

Code converter

Output code

Example: BCD to Excess-3 Code Converter.

Input: BCD digit Output: Excess-3 digit

BCD-to-Excess-3 Code Converter

Truth table:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BCD B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Excess-3 W X Y Z 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X

K-maps:
AB CD

C 01 1 X X 1 11 10 1 X X 1 X X
AB

CD

C 01 1 11 10 1 1 B

00

00

00 01 A 11 B A

00 01 1 11 10 X

X 1

X X

X X

10 1

W
CD

X
C
CD

C 01 11 10 1 1 X X X D X X B

AB

00

01

11 10 1 1 B

AB

00

00 1 01 1 A 11 X X

00 1 01 1 A 11 X

X X D

X X

10 1

10 1

BCD-to-Excess-3 Code Converter

AB CD

C 01 1 X X 1 D 11 10 1 X X 1 X X
AB

CD

C 01 1 11 10 1 1 B

00

00

00

00 B A

W = A + BC + BD X = B'C + B'D + BC'D'

01
A 11

01 1
11 10 X X 1 D X X X X

10 1

W
CD

X
C
CD

Y = CD + C'D'
C 01 11 10 1 1 X X X D X X B 00

AB

00

01

11 10 1 1 B

AB

00 1 01 1 A 11 X X

00 1 01 1 A 11 X

Z = D'

X X D

X X

10 1

10 1

Block-Level Design Method

More complex circuits can also be built using block-level
method.

In general, block-level design method (as opposed to

gate-level design) relies on algorithms or formulae of the circuit, which are obtained by decomposing the main problem to sub-problems recursively (until small enough to be directly solved by blocks of circuits).

Simple examples using 4-bit parallel adder as building

blocks:
(1) BCD-to-Excess-3 Code Conversion (2) 16-Bit Parallel Adder (3) Adder cum Subtractor

4-bit Parallel Adder

Consider a circuit to add two 4-bit numbers together and a
carry-in, to produce a 5-bit result:
X4 X3 X2 X1 Y4 Y3 Y2 Y1

C5

4-bit Parallel Adder

C1
Black-box view of 4-bit parallel adder

S4 S3 S2 S1

5-bit result is sufficient because the largest result is:

(1111)2+(1111)2+(1)2 = (11111)2

4-bit Parallel Adder

SSI design technique should not be used.

Truth table for 9 inputs very big, i.e. 29=512 entries:

X4X3X2X1 0 0 0 0 0 0 0 0 0 0 0 0 ... 0 1 0 1 ... 1 1 1 1 Y4Y3Y2Y1 0 0 0 0 0 0 0 0 0 0 0 1 ... 1 1 0 1 ... 1 1 1 1 C1 0 1 0 ... 1 ... 1 C5 0 0 0 ... 1 ... 1 S4S3S2S1 0 0 0 0 0 0 0 1 0 0 0 1 ... 0 0 1 1 ... 1 1 1 1

Simplification very complicated.

4-bit Parallel Adder

Alternative design possible. Addition formulae for each pair of bits (with carry in),
Ci+1Si = Xi + Yi + Ci has the same function as a full adder. Ci+1 = Xi Yi + (Xi Yi ) Ci

Si = Xi Yi Ci

4-bit Parallel Adder

Cascading 4 full adders via their carries, we get:
Y4 X4
C4

Y3 X3
C3

Y2 X2
C2

Y1 X 1

C5

FA

FA

FA

FA

C1

S4
Input
Output

S3

S2

S1

Parallel Adders
Note that carry propagated by cascading the carry from
one full adder to the next.

Called Parallel Adder because inputs are presented

simultaneously (in parallel). Also, called Ripple-Carry Adder.

BCD-to-Excess-3 Code Converter

Excess-3 code can be
converted from BCD code using truth table: Gate-level design can be used since only 4 inputs.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BCD B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Excess-3 W X Y Z 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X

However, alternative design possible.

Use problem-specific formulae:
(0011)2 Excess-3 Code = BCD Code +

BCD-to-Excess-3 Code Converter

Excess-3 Code = BCD Code + (0011)2

Block-level circuit:
BCD code
X4 X3 X2 X1 0 0 1 1

unused Cout

4-bit Parallel Adder

Cin
0

Y4 Y3 Y2 Y1

S4 S3 S2 S1

Excess-3 code

A BCD-to-Excess-3 Code Converter

16-bit Parallel Adder

Larger parallel adders can be built from smaller ones. Example: a 16-bit parallel adder can be constructed from
four 4-bit parallel adders:
X16..X13 Y16..Y13
4 4

X12..X9 Y12..Y9
4 4

X8..X5
4

Y8..Y5
4

X4..X1
4

Y4..Y1
4

C17

4-bit // adder
4

C13

4-bit // adder
4

C9

4-bit // adder
4

C5

4-bit // adder
4

C1

S16..S13

S12..S9

S8..S5

S4..S1

A 16-bit parallel adder

16-bit Parallel Adder

Shortened notation for multiple lines.
4

is a shortened notation for S4 S3 S2 S1

S4 .. S1

16-bit parallel adder ripples carry from one 4-bit block to the next. Such ripple-carry circuits are slow because of long delays needed to propagate the carries.

4-bit Parallel Adder cum Subtractor

*Optional

Subtraction can be performed through addition using 2scomplement numbers.

Hence, we can design a circuit which can perform both

addition and subtraction, using a parallel adder.
X4 X3 X2 X1 Y4 Y3 Y2 Y1

4-bit adder cum subtractor

S: control signal for add/subtract

Result: either X+Y or X-Y

4-bit Parallel Adder cum Subtractor

The control signal S=0 means add
S=1 means subtract

Recall that:
X-Y = X + (-Y) = X + (2s complement of Y) = X + (1s complement of Y) +1 X+Y = X + (Y)

4-bit Parallel Adder cum Subtractor

Design requires:
(i) XOR gates:
Y S=0 Y Y S=1 Y'

such that: output = Y when S=0 = Y' when S=1 (ii) S connected to carry-in.

4-bit Parallel Adder cum Subtractor

Adder cum subtractor circuit:
Y4 Y3 Y2 Y1 X4 X3 X2 X1 S

Cout

4-bit parallel adder

Cin

Analysis: If S=1, then X + (1's complement of Y) +1 appears as the result. If S=0, then X+Y appears as the result.

S4 S3 S2 S1

A 4-bit adder cum subtractor

Arithmetic Circuits: Adders

Half adder
x 0 0 1 1
x y' x' y x y x y x' y' x y

Revision
C 0 0 0 1 S 0 1 1 0

y 0 1 0 1

S Input bits
X
Y

S
Cout

Sum
Carry

Output bits

S = xy' + x'y

x' y' x y

S = (C+x'y')' C

C x y

S = (x+y)(x'+y')

S=xy C

Arithmetic Circuits: Adders

Full adder
Revision
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 C 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1

S Input bits
yz x

A B Cin

S Cout
yz x

Sum Carry

Output bits

X' y' z x' y z' x y' z' x y z x y x z y z

00 01 11 10
1

00 01 11 10
1 1

1 1 1 1 C = xy + xz + yz

1 1 1 S = x'y'z + x'yz' + xy'z' + xyz

x y

x y S = (xy)z xy C = xy + (xy)z

Arithmetic Circuits: Parallel Adders

Example: Adding two 4-bit numbers
Subscript i Input carry Augend Addend Sum Output carry 4 0 1 0 1 0 3 1 0 0 1 0 2 1 1 1 1 1 1 0 Ci 1 Ai 1 Bi 0 Si 1 Ci+1

Revision

2 ways: Serial (one FA) Parallel (n FAs for n bits)

Y4 X4 Y3 X3 Y2 X2 Y1 X1

C4
C5 Binary no. A Binary no. B Input carry FA FA

C3
FA

C2
FA C1

S
S 4-bit sum

S4

S3

S2

S1

Y Cin Cout Output carry

Arithmetic Circuits: Cascading Adders

Revision

4-bit parallel adder:

cascade 4 full adders classical method: 9 input variables 29 = 512 rows in truth

table!

Cascading method can be extended to larger numbers,

example: 16-bit parallel adder.
X16..X13 Y16..Y13
4 4

X12..X9 Y12..Y9
4 4

X8..X5
4

Y8..Y5
4

X4..X1
4

Y4..Y1
4

C17

4-bit // adder
4

C13

4-bit // adder
4

C9

4-bit // adder
4

C5

4-bit // adder
4

C1

S16..S13

S12..S9

S8..S5

S4..S1

Arithmetic Circuits: Cascading Adders

Application: 6-person voting system.
Use FAs and a 4-bit binary parallel adder. Each FA can sum up to 3 votes.
S Voter 1
A B Cin S Cout

Voter 2
Voter 3

1 2 3 4 1 2 3 4

S
A

S
B

Full-adder 1 S Voter 4 Voter 5 Voter 6

A B Cin S Cout

1 2 3 4

3-bit Output

Cout

Cin

Parallel adder

Full-adder 2

Arithmetic Circuits: Adder-Subtractor

Revision

Make use of 2s complement:

X - Y = X + (-Y)

2s complement of Y = Inverting bits in Y and plus 1.

Y4 Y3 Y2 Y1 S

X4 X3 X2 X1
Z4 Z3 Z2 Z1

Zi = S.Yi' + S'.Yi
When S=0, Cin=0, Zi = Yi S = X + Y When S=1, Cin=1, Zi = Yi' S = X + Y' + 1

Cout

4-bit parallel adder

Cin

S4 S3 S2 S1

Arithmetic Circuits: Comparator

Magnitude comparator: compares 2 values A and B, to
see if A>B, A=B or A<B.

Classical method requires 22n rows in truth table! We exploit regularity.

How do we compare two 4-bit values A (a3a2a1a0) and B

(b3b2b1b0)? If (a3 > b3) then A > B If (a3 < b3) then A < B If (a3 = b3) then if (a2 > b2) .

Arithmetic Circuits: Comparator

Let A = A3A2A1A0 , B = B3B2B1B0; xi = Ai.Bi + Ai'.Bi'
A3 B3 A2 B2 A1 B1 x2

x3
A3.B3'

A3'.B3 A3'.B3 + x3.A2'.B2 + x3.x2.A1'.B1 + x3. x2.x1.A0'.B0

(A < B)
x1 A3.B3' + x3.A2.B2' + x3.x2.A1.B1' + x3. x2.x1.A0.B0' A0 B0 (A = B) x3. x2.x1.x0 x0 (A > B)

Arithmetic Circuits: Comparator

0 1 1 0 1 0 1 0

A3 A2 A1 A0 B3 B2 B1 B0

4-bit comp

(A < B) (A > B) (A = B)

1 0 0

Block diagram of a 4-bit magnitude comparator

Propagation Delay
Every logic gate experiences some delay (though very
small) in propagating signals forward.

This delay is called Gate (Propagation) Delay. Formally, it is the average transition time taken for the
output signal of the gate to change in response to changes in the input signals.

Three different propagation delay times associated with a

logic gate:
tPHL: output changing from the High level to Low level tPLH: output changing from the Low level to High level tPD=(tPLH + tPHL)/2

(average propagation delay)

Propagation Delay
Input Output

Input
L H L tPHL tPLH

Output

Propagation Delay
A B C

Ideally, no
delay:
1
0 1 0 1 0

In reality, output signals normally lag behind input signals:

1
0 1

Signal for A

Signal for A

Signal for B Signal for C time

0 1 0

Signal for B Signal for C time

Calculation of Circuit Delays

Amount of propagation delay per gate depends on:
(i) gate type (AND, OR, NOT, etc)

(ii) transistor technology used (TTL,ECL,CMOS etc),

(iii) miniaturisation (SSI, MSI, LSI, VLSI)

To simplify matters, one can assume

(i) an average delay time per gate, or (ii) an average delay time per gate-type.

Propagation delay of logic circuit

= longest time it takes for the input signal(s) to propagate to the output(s). = earliest time for output signal(s) to stabilise, given that input signals are stable at time 0.

Calculation of Circuit Delays

In general, given a logic gate with delay, t.
t1 t2 : tn
Logic Gate max (t1, t2, ..., tn ) + t

If inputs are stable at times t1,t2,..,tn, respectively; then the earliest time in which the output will be stable is: max(t1, t2, .., tn) + t

To calculate the delays of all outputs of a combinational circuit, repeat above rule for all gates.

Calculation of Circuit Delays

As a simple example, consider the full adder circuit where
all inputs are available at time 0. (Assume each gate has delay t.)
X Y
0 0 max(0,0)+t = t max(t,0)+t = 2t

S
t 2t

max(t,2t)+t = 3t

where outputs S and C, experience delays of 2t and 3t, respectively.

Calculation of Circuit Delays

More complex example: 4-bits parallel adder.
Y4 X 4 0 0 C4 Y3 X3 0 0 C3 Y2 X2 0 0 C2 Y1 X 1 0 0

C5

FA

FA

FA

FA

C1

S4

S3

S2

S1

Calculation of Circuit Delays

Analyse the delay for the repeated block:
Xi Yi Ci

0 0 mt

Full Adder

Si Ci+1

where Xi, Yi are stable at 0t, while Ci is assumed to be stable at mt.

Performing the delay calculation gives:

Xi 0 Yi 0
max(0,0)+t = t max(t,mt)+t

Si
t
max(t,mt)+t max(t,mt)+2t

Ci+1 Ci
mt

Calculation of Circuit Delays

Calculating:
When i=1, m=0: S1 = 2t and C2 = 3t. When i=2, m=3: S2 = 4t and C3 = 5t. When i=3, m=5: S3 = 6t and C4 = 7t. When i=4, m=7: S4 = 8t and C5 = 9t.

In general, an n-bit ripple-carry parallel adder will

experience:
Sn = ((n-1)*2+2)t Cn+1 = ((n-1)*2+3)t

as their delay times. Propagation delay of ripple-carry parallel adders is proportional to the number of bits it handles. Maximum Delay: ((n-1)*2+3)t

Faster Circuits
Three ways of improving the speed of these circuits:
(i) Use better technology (e.g. ECL faster than TTL gates), BUT (a) faster technology is more expensive, needs more power, lower-level of integrations. (b) physical limits (e.g. speed of light, size of atom). (ii) Use gate-level designs to two-level circuits! (use sum-

of-products/product-of-sums) BUT
(a) complicated designs for large circuits. (b) product/sum terms need MANY inputs!

(iii) Use clever look-ahead techniques BUT there are

additional costs (hopefully reasonable).

Look-Ahead Carry Adder*

Consider the full adder:
Xi Yi
Pi Si Gi Ci+1 Ci

where intermediate signals are labelled as Pi, Gi, and defined as:
Pi = XiYi Gi = Xi.Yi

The outputs, Ci+1,Si, in terms of Pi ,Gi ,Ci , are:

Si = Pi Ci Ci+1 = Gi + Pi.Ci (1) (2)

If you look at equation (2),

Gi = Xi.Yi is a carry generate signal Pi = Xi Yi is a carry propagate signal

Look-Ahead Carry Adder

For 4-bit ripple-carry adder, the equations to obtain four
carry signals are:
Ci+1 = Gi + Pi.Ci Ci+2 = Gi+1 + Pi+1.Ci+1 Ci+3 = Gi+2 + Pi+2.Ci+2 Ci+4 = Gi+3 + Pi+3.Ci+3

These formula are deeply nested, as shown here for Ci+2:

Ci Pi Gi

Ci+1

Pi+1
Ci+2 Gi+1

4-level circuit for Ci+2 = Gi+1 + Pi+1.Ci+1

Look-Ahead Carry Adder

Nested formula/gates cause ripple-carry propagation

delay. Can reduce delay by expanding and flattening the formula for carries. For example, Ci+2
Ci+2 = Gi+1 + Pi+1.Ci+1 = Gi+1 + Pi+1.(Gi + Pi.Ci ) = Gi+1 + Pi+1.Gi + Pi+1.Pi.Ci

New faster circuit for Ci+2

Pi+1 Gi Pi+1 Gi+1 Ci+2 Ci Pi

Look-Ahead Carry Adder

Other carry signals can also be similarly flattened.
Ci+3= Gi+2 + Pi+2Ci+2 = Gi+2 + Pi+2(Gi+1 + Pi+1Gi + Pi+1PiCi) = Gi+2 + Pi+2Gi+1 + Pi+2Pi+1Gi + Pi+2Pi+1PiCi Ci+4 = Gi+3 + Pi+3Ci+3 = Gi+3 + Pi+3(Gi+2 + Pi+2Gi+1 + Pi+2Pi+1Gi + Pi+2Pi+1PiCi) = Gi+3 + Pi+3Gi+2 + Pi+3Pi+2Gi+1 + Pi+3Pi+2Pi+1Gi + Pi+3Pi+2Pi+1PiCi

Notice that formulae gets longer with higher carries. Also, all carries are two-level sum-of-products expressions, in terms of the generate signals, Gs, the propagate signals, Ps, and the first carry-in, Ci.

Look-Ahead Carry Adder

We employ the
look-ahead formula in this lookahead-carry adder circuit:

Look-Ahead Carry Adder

The 74182 IC chip allows
faster lookahead adder to be built.

Maximum propagation
delay is 4t (t to get generate & propagate signals, 2t to get the carries and t for the sum signals) where t is the average gate delay.

Binary Multipliers
The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding

0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 3 4 5 6 7 8 9 2 0 2 4 6 8 10 12 14 16 18 3 0 3 6 9 12 15 18 21 24 27 4 0 4 8 12 16 20 24 28 32 36 5 0 5 10 15 20 25 30 35 40 45 6 0 6 12 18 24 30 36 42 48 54 7 0 7 14 21 28 35 42 49 56 63 8 0 8 16 24 32 40 48 56 64 72 9 0 9 18 27 36 45 54 63 72 81

0 0

1 0

Youve got to be kidding It cant be that easy

Reading: Study Chapter 3.

Comp 411 Spring 2008 02/26/2008 L11 Multiplication Division 58

The Binary Multiplication Table

Binary Multiplication
0 0 0 1 0 1 Binary multiplication is implemented using the same basic longhand algorithm that you learned in grade school. A3 x B3 A3B0 A3B1 A3B2 A2B2 A1B3 A2B1 A1B2 A0B3

Hey, that looks like an AND gate

X 0 1

A2 B2
A2B0 A1B1 A0B2

A1 B1 A1B0 A0B1

A0 B0 A0B0

AjBi is a partial product

A3B3

A2B3

Multiplying N-digit number by M-digit number gives (N+M)-digit result

Easy part: forming partial products (just an AND gate since B I is either 0 or 1) Hard part: adding M, N-bit partial products
Comp 411 Spring 2008 02/26/2008 L11 Multiplication Division 59

Multiplication: Implementation
Multiplicand Shift left 64 bits
Multiplier0 = 1 1. Te st Multiplier0 Multiplier0 = 0 Sta rt

64-bit ALU

Multiplier Shift right 32 bits

Product Write 64 bits

Control test

1a. Add multiplicand to product and place the re sult in Product re gi ster

2. Shift the Multiplicand register le ft 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

No: < 32 re pe titio ns

Ye s: 32 repetitio ns

Done

Comp 411 Spring 2008

02/26/2008

L11 Multiplication Division 60

Second Version
Start Mul ti pli cand 32 bits Multiplier0 = 1 32-bit ALU Mul tiplier Shift right 32 bits 1. Test Multiplier0 Multiplier0 = 0

Pro duct
64 bits

Shi ft right Write

Control test

1a. Add multiplicand to the le ft half of the product and place the re sult in the le ft half of the Product register

2. Shift the Product register right 1 bit

3. Shift the Multiplier registe r right 1 bit

32nd repetition?

No : < 32 repetitions

Yes: 32 repetitions

Done

Comp 411 Spring 2008

02/26/2008

L11 Multiplication Division 61

Example for second version

Iteration 0 1 Step Initial Multiplier Multiplican d 1011 0010 0010 Product 0000 0000 0010 0000 0001 0000

Test true 1011 shift right 0101

2
3 4

Test true 0101 shift right 0010

Test false 0010 shift right 0001 Test true 0001 shift right 0000

0010
0010 0010

0011 0000 0001 1000

0001 1000 0000 1100 0010 1100 0001 0110

Comp 411 Spring 2008

02/26/2008

L11 Multiplication Division 62

Final Version
Start

Multiplicand 32 bits
Product0 = 1 1. Test Product0 Product0 = 0

32-bit ALU
1a. Add multiplicand to the left half of the product and place the result in the left half of the Product register

Product 64 bits

Shift right Write

Control test

2. Shift the Product register right 1 bit

The trick is to use the lower half of the product to hold the multiplier during the operation.

32nd repetition?

No: < 32 repetitions

Yes: 32 repetitions

Done

Comp 411 Spring 2008

02/26/2008

L11 Multiplication Division 63

What about the sign?

Positive numbers are easy. How about negative numbers? (see Booth coding in textbook)

Comp 411 Spring 2008

02/26/2008

L11 Multiplication Division 64

Faster Multiply
A1 & B A0 & B

A2 & B

A2 & B

A31 & B

P32-P63

P31

P2

P1

P0

Comp 411 Spring 2008

02/26/2008

L11 Multiplication Division 65

Simple Combinational Multiplier

tPD = 10 * tPD,FA
not 16
Co

HA
S

A B Co

HA
S

A B Co

HA
S

A B Co

HA
S

A B

tPD = (2*(N-1) + N) * tPD,FA Components N * HA N(N-1) * FA

The Logic A B of a HalfAdder
CO S NB: this circuit only works for nonnegative operands
Comp 411 Spring 2008 02/26/2008 L11 Multiplication Division 66

Carry-Save Combinational Multiplier

Observation: Rather than propagating the sums across each row, the carries can instead be forwarded onto the next column of the following row

These Adders can be removed, and the AND gate outputs tied directly to the Carry inputs of the next stage.

tPD = 8 * tPD,FA tPD = (N+N) * tPD,FA Components N * HA N2 * FA

This small improveme nt in performanc e hardly seems worth the effort, however, this design is easier to pipeline.

Comp 411 Spring 2008

02/26/2008

L11 Multiplication Division 67

Division
Start 1. Subtract Divisor from the Remainder leave the result in the Remainder >=0 <0

Test Remainder

Shift Quotient to the left set its rightmost bit = 1

Restore Remainder by adding Divisor Shift Quotient to the left set its rightmost bit = 0

Shift Divisor Register right 1 bit

Repeat 33 times

Comp 411 Spring 2008

02/26/2008

L11 Multiplication Division 68

Digital Logic
7400 Series parts found in the evaluation lib:
7400 7401 7402 7403 7404 7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7416 7417 7420 7422 Quadruple 2-input Positive-Nand Gates Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs Quadruple 2-input Positive-Nor Gates Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs Hex Inverters Hex Inverters with Open-Collector Outputs Hex Inverter Buffers/Drivers with Open-Collector High-Voltage Outputs Hex Buffers/Drivers with Open-Collector High-Voltage Outputs Quadruple 2-input Positive-And Gates Quadruple 2-input Positive-And Gates with Open-Collector Outputs Triple 3-input Positive-Nand Gates Triple 3-input Positive-And Gates Triple 3-input Positive-Nand Gates with Open-Collector Outputs Dual 4-input Positive-Nand Schmitt Triggers Hex Schmitt-Trigger Inverters Hex Inverter Buffers/Drivers with Open-Collector High-Voltage Outputs Hex Buffers/Drivers with Open-Collector High-Voltage Outputs Dual 4-input Positive-Nand Gates Dual 4-input Positive-Nand Gates with Open-Collector Outputs

69

7400 Series parts found in the evaluation library (eval.slb):

7423 Dual 4-input Nor Gates with Strobe 7425 Dual 4-input Nor Gates with Strobe 7426 High-Voltage Interface Positive-Nand Gates 7427 Triple 3-input Positive-Nor Gates 7428 Quadruple 2-input Positive-Nor Buffers 7430 8-input Positive-Nand Gates 7432 Quadruple 2-input Positive-Or Gates 7433 Quadruple 2-input Positive-Nor Buffers w/ Open-Collector Outputs 7437 Quadruple 2-input Positive-Nand Buffers 7438 Quadruple 2-input Positive-Nand Buffers w/ Open-Collector Outputs 7439 Quadruple 2-input Positive Nand Buffers with Open-Collector Outputs 7440 Dual 4-input Positive-Nand Buffers 7442A DECODER BCD-DECIMAL 4-10 LINE 7443A DECODER EXCESS-3-DECIMAL 4-10 LINE 7444A DECODER GRAY-DECIMAL 4-10 LINE 7445 DECODER/DRIVER BCD-DECIMAL WITH OPEN COLLECTOR OUTPUTS 7446A DECODER/DRIVER BCD-7 SEGMENT WITH OPEN-COLLECTOR OUTPUTS 7447A DECODER/DRIVER BCD-7 SEGMENT WITH OPEN COLLECTOR OUTPUTS
70

Lecture #8

EGR 277 Digital Logic

7400 Series parts found in the evaluation library (eval.slb):

7448 DECODER/DRIVER BCD-7 SEGMENT WITH INTERNAL PULLUPS 7449 DECODER/DRIVER BCD-7 SEGMENT WITH OPEN-COLLECTOR OUTPUTS 7450 Dual 2-wide 2-input And-Or-Invert Gates 7451 And-Or-Invert Gates 7453 Expandable 4-wide And-Or-Invert Gates 7454 4-wide And-Or-Invert Gates 7460 Dual 4-input Expanders 7470 And-Gated J-K Positive-Edge-Triggered Flip-Flops with Preset & Clear 7472 And Gated J-K Master-Slave Flip-Flops with Preset and Clear 7473 Dual J-K Flip-Flops with Clear 7474 Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear 7475 4-bit bistable latches (dual 2-bit common clock4-bit bistable latches ) 7476 Dual J-K Flip-Flops with Preset and Clear 7477 4-bit bistable latches 7482 2-BIT BINARY FULL ADDERS 7483A 4-BIT BINARY FULL ADDERS WITH FAST CARRY 7485 4-BIT MAGNITUDE COMPARATOR 7486 Quadruple 2-input Exclusive-Or Gates
71

7400 Series parts found in the evaluation library (eval.slb):

7490A COUNTER DECADE 4-BIT, ASYNCHRONOUS 7491A 8-BIT SHIFT REGISTERS 7492A COUNTER DIVIDE-BY-12 4-BIT, ASYNCHRONOUS 7493A COUNTER BINARY 4-BIT, ASYNCHRONOUS 7494 4-BIT SHIFT REGISTERS 7495A 4-BIT PARALLEL SHIFT REGISTERS 7496 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS 74100 8-Bit Bistable Latches 74107 Dual J-K Flip-Flops with Clear 74109 Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Preset & Clear 74110 And-Gated J-K Master-Slave Flip-Flops with Data Lockout 74111 Dual J-K Master-Slave Flip-Flops with Data Lockout 74121 Non-retriggerable Monostable Multivibrator w/Schmitt-Trigger Inputs 74122 Retriggerable Monostable Multivibrator 74123 Retriggerable Monostable Multivibrator 74125 Quadruple Bus Buffer with 3-state Outputs 74126 Quadruple Bus Buffer with 3-state Outputs 74128 Line Drivers 74132 Quadruple 2-input Positive-Nand Schmitt Triggers

72

7400 Series parts found in the evaluation library (eval.slb):

74136 Quadruple 2-input Exclusive-Or Gates with Open-Collector Outputs 74145 DECODER/DRIVER BCD-DECIMAL WITH OPEN COLLECTOR OUTPUTS 74147 PRIORITY ENCODER 10-4 LINE 74148 PRIORITY ENCODER 8-3 LINE 74151A MULTIPLEXER/DATA SELECTOR 8-1 LINE 74151A MULTIPLEXER/DATA SELECTOR 8-1 LINE 74154 DECODER/DEMULTIPLEXER 4-16 LINE 74155 DECODER/DEMULTIPLEXER 2-4 LINE 74156 DECODER/DEMULTIPLEXER 2-4 LINE WITH OPEN COLLECTOR OUTPUTS 74157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS 74159 DECODER/DEMULTIPLEXER 4-16 LINE WITH OPEN COLLECTOR OUTPUTS 74160 Synchronous 4-bit Decade Counters with asynchronous clear 74161 Synchronous 4-bit Binary Counter with Direct Clear 74162 Synchronous 4-bit Decade Counters with synchronous clear 74163 Synchronous 4-bit Binary Counter 74164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS 74173 REGISTERS D-TYPE 4-BIT WITH 3-STATE OUTPUTS 74174 HEX D-TYPE FLIP-FLOPS WITH CLEAR 73 74175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR etc.

Thank You