VLSI Design

Lecture 3a:
Nonideal Transistors
Outline
Transistor I-V Review
Nonideal Transistor Behavior
Velocity Saturation
Channel Length Modulation
Body Effect
Leakage
Temperature Sensitivity
Process and Environmental Variations
Process Corners
Ideal Transistor I-V
Shockley 1
st
order transistor models
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
|
|

<

| |
= <
|
\ .

>

Ideal nMOS I-V Plot

180 nm TSMC process

Ideal Models
| = 155(W/L) A/V
2
V
t
= 0.4 V
V
DD
= 1.8 V
I
ds
(A)
V
ds
0 0.3 0.6 0.9 1.2 1.5 1.8
100
200
300
400
V
gs
= 0.6
V
gs
= 0.9
V
gs
= 1.2
V
gs
= 1.5
V
gs
= 1.8
0
Simulated nMOS I-V Plot
180 nm TSMC process
BSIM 3v3 SPICE models
What differs?
V
ds
0 0.3 0.6 0.9 1.2 1.5
V
gs
= 1.8
I
ds
(A)
0
50
100
150
200
250
V
gs
= 1.5
V
gs
= 1.2
V
gs
= 0.9
V
gs
= 0.6
Simulated nMOS I-V Plot
180 nm TSMC process
BSIM 3v3 SPICE models
What differs?
Less ON current
No square law
Current increases
in saturation
V
ds
0 0.3 0.6 0.9 1.2 1.5
V
gs
= 1.8
I
ds
(A)
0
50
100
150
200
250
V
gs
= 1.5
V
gs
= 1.2
V
gs
= 0.9
V
gs
= 0.6
Velocity Saturation
We assumed carrier velocity is proportional to E-field
v = E
lat
= V
ds
/L
At high fields, this ceases to be true
Carriers scatter off atoms
Velocity reaches v
sat
Electrons: 6-10 x 10
6
cm/s
Holes: 4-8 x 10
6
cm/s
Better model
E
sat 0
0
slope =
E
lat
v
2E
sat
3E
sat
v
sat
v
sat
/ 2
lat
sat sat
lat
sat

1
E
v v E
E
E
= =
+
Vel Sat I-V Effects
Ideal transistor ON current increases with V
DD
2


Velocity-saturated ON current increases with V
DD


Real transistors are partially velocity saturated
Approximate with o-power law model
I
ds
V
DD
o

1 < o < 2 determined empirically
( )
( )
2
2
ox
2 2
gs t
ds gs t
V V
W
I C V V
L
|

= =
( )
ox max ds gs t
I CWVVv =
o-Power Model
I
ds
(A)
V
ds
0 0.3 0.6 0.9 1.2 1.5 1.8
100
200
300
400
V
gs
= 0.6
V
gs
= 0.9
V
gs
= 1.2
V
gs
= 1.5
V
gs
= 1.8
0
o-law
Simulated
Shockley
0 cutoff
linear
saturation
gs t
ds
ds dsat ds dsat
dsat
dsat ds dsat
V V
V
I I V V
V
I V V

<

= <

>

( )
( )
/ 2
2
dsat c gs t
dsat v gs t
I P V V
V P V V
o
o
|
=
=
Channel Length Modulation
Reverse-biased p-n junctions form a depletion
region
Region between n and p with no carriers
Width of depletion L
d
region grows with reverse bias
L
eff
= L L
d
Shorter L
eff
gives more current
I
ds
increases with V
ds
Even in saturation
n+
p
Gate Source Drain
bulk Si
n+
V
DD GND
V
DD
GND
L
L
eff
Depletion Region
Width: L
d
Chan Length Mod I-V

= channel length modulation coefficient
not feature size
Empirically fit to I-V characteristics

( )
( )
2
1
2
ds gs t ds
I V V V
|
= +
I
ds
(A)
V
ds
0 0.3 0.6 0.9 1.2 1.5 1.8
100
200
300
400
V
gs
= 0.6
V
gs
= 0.9
V
gs
= 1.2
V
gs
= 1.5
V
gs
= 1.8
0
Body Effect
V
t
: gate voltage necessary to invert channel
Increases if source voltage increases
because source is connected to the channel
Increase in V
t
with V
s
is called the body effect
Body Effect Model


|
s
= surface potential at threshold

Depends on doping level N
A
And intrinsic carrier concentration n
i
= body effect coefficient
( )
0 t t s sb s
VV V | | =+ +
2 ln
A
s T
i
N
v
n
| =
si
ox
si
ox ox
2q
2q
A
A
N
t
N
C
c
c
c
= =
OFF Transistor Behavior
What about current in cutoff?
Simulated results
What differs?
Current doesnt go
to 0 in cutoff
V
t
Sub-
threshold
Slope
Sub-
threshold
Region
Saturation
Region
V
ds
= 1.8
I
ds
V
gs
0 0.3 0.6 0.9 1.2 1.5 1.8
10 pA
100 pA
1 nA
10 nA
100 nA
1 A
10 A
100 A
1 mA
Leakage Sources
Subthreshold conduction
Transistors cant abruptly turn ON or OFF
Junction leakage
Reverse-biased PN junction diode current
Gate leakage
Tunneling through ultrathin gate dielectric
Subthreshold leakage is the biggest source in
modern transistors
Subthreshold Leakage
Subthreshold leakage exponential with V
gs



n is process dependent, typically 1.4-1.5
0
e 1 e
gs t
ds
T T
V V
V
nv v
ds ds
I I


| |
=
|
|
\ .
2 1.8
0
e
ds T
I v | =
DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect V
t


High drain voltage causes subthreshold
leakage to ________.
ttdsVVVq'=
t t ds
V V V q
'
=
DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect V
t


High drain voltage causes subthreshold
leakage to increase.
ttdsVVVq'=
t t ds
V V V q
'
=
Junction Leakage
Reverse-biased p-n junctions have some
leakage

I
s
depends on doping levels
And area and perimeter of diffusion regions
Typically < 1 fA/m
2
e 1
D
T
V
v
D S
I I
| |
=
|
|
\ .
n well
n+ n+ n+ p+ p+ p+
p substrate
Gate Leakage
Carriers may tunnel thorough very thin gate oxides
Predicted tunneling current (from [Song01])






Negligible for older processes
May soon be critically important
V
DD
0 0.3 0.6 0.9 1.2 1.5 1.8
J
G

(
A
/
c
m
2
)
10
-9
10
-6
10
-3
10
0
10
3
10
6
10
9
t
ox
0.6 nm
0.8 nm
1.0 nm
1.2 nm
1.5 nm
1.9 nm
V
DD
trend
Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces V
t
I
ON
___________ with temperature
I
OFF
___________ with temperature
Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces V
t
I
ON
decreases with temperature
I
OFF
increases with temperature
V
gs
ds
I
increasing
temperature
So What?
So what if transistors are not ideal?
They still behave like switches.
But these effects matter for
Supply voltage choice
Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation
Parameter Variation
Transistors have uncertainty in parameters
Process: L
eff
, V
t
, t
ox
of nMOS and pMOS
Vary around typical (T) values
Fast (F)
L
eff
: ______
V
t
: ______
t
ox
: ______
Slow (S): opposite
Not all parameters are independent
for nMOS and pMOS
nMOS
p
M
O
S
fast slow
s
l
o
w
f
a
s
t
TT
FF
SS
FS
SF
Parameter Variation
Transistors have uncertainty in parameters
Process: L
eff
, V
t
, t
ox
of nMOS and pMOS
Vary around typical (T) values
Fast (F)
L
eff
: short
V
t
: low
t
ox
: thin
Slow (S): opposite
Not all parameters are independent
for nMOS and pMOS
nMOS
p
M
O
S
fast slow
s
l
o
w
f
a
s
t
TT
FF
SS
FS
SF
Environmental Variation
V
DD
and T also vary in time and space
Fast:
V
DD
: ____
T: ____
70 C 1.8 T
S
F
Temperature Voltage Corner
Environmental Variation
V
DD
and T also vary in time and space
Fast:
V
DD
: high
T: low
70 C 1.8 T
125 C 1.62 S
0 C 1.98 F
Temperature Voltage Corner
Process Corners
Process corners describe worst case
variations
If a design works in all corners, it will probably
work for any variation.
Describe corner with four letters (T, F, S)
nMOS speed
pMOS speed
Voltage
Temperature
Important Corners
Some critical simulation corners include
Pseudo-nMOS
Subthrehold
leakage
Power
Cycle time
Temp V
DD
pMOS nMOS Purpose
Important Corners
Some critical simulation corners include
? ? F S Pseudo-nMOS
S F F F Subthrehold
leakage
F F F F Power
S S S S Cycle time
Temp V
DD
pMOS nMOS Purpose