An Efficient Power Reduction Technique For VLSI Circuits

Presented By Reg. No. Under the Guidance of MILON MAHAPATRA 1581110065 Dr.M.Malathi , Professor and Mr.B.Srinath , Assistant Professor

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Idea in brief

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C1

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C2

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C3

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D D D D

D
D

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D D D D

D
D

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D D D D

D
D

After knowing maximum path delay range, adjust delay in critical path to reduce the possibility of simultaneous switching
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C1

Dmax Dmax

C4
Dmax Dmax

C2

C3

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Calculate the delay value required for all input to adjust the switching time of all gates, such that by controlling delay of input we can control the switching of all gates
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Algorithm Partitioning using clustering

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Algorithm Partitioning using clustering & Scheduling

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Algorithm Partitioning using clustering & Scheduling

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Algorithm Partitioning using clustering & Scheduling

Calculated delay value of all input

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Algorithm Partitioning using clustering & Scheduling Simulation Verilog program

Calculated delay value of all input

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Algorithm Partitioning using clustering & Scheduling Simulation Verilog program

Calculated delay value of all input

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Algorithm Partitioning using clustering & Scheduling Simulation Verilog program Layout generation Automatically using Microwind

Calculated delay value of all input

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Algorithm Partitioning using clustering & Scheduling Simulation Verilog program Layout generation Automatically using Microwind

Calculated delay value of all input

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Algorithm Partitioning using clustering & Scheduling Simulation Verilog program Layout generation Automatically using Microwind In layout, input Assignment with Calculated delay

Calculated delay value of all input

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Cont
Algorithm Partitioning using clustering & Scheduling Simulation Verilog program Layout generation Automatically using Microwind In layout, input Assignment with Calculated delay

Calculated delay value of all input

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Cont
Algorithm Partitioning using clustering & Scheduling Simulation Verilog program Layout generation Automatically using Microwind In layout, input Assignment with Calculated delay

Calculated delay value of all input

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Algorithm Partitioning using clustering & Scheduling Simulation Verilog program Layout generation Automatically using Microwind In layout, input Assignment with Calculated delay

Calculated delay value of all input

Simulation for power dissipation

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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work Conclusions References
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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work Conclusions References
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Objective
To develop a peak power reduction technique for VLSI circuits by using path clustering and scheduling algorithm.

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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work Conclusions References
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Clustering Algorithm
Perform Edge Coarsening (EC)
Visit nodes and break ties in alphabetical order

Hyper Graph

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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work Conclusions References
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Benchmark C17 circuit diagram

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Cont..

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Cont..

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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work Conclusions References
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Overview of phase 1
Designing of a parser to convert verilog program format into C++ language format as per requirement. Developing a programming model to execute clustering algorithm concept. This was done partly. Those were

1. Finding the total net list in a benchmark. 2. Finding the numbers of interconnection which form clusters. 3. List the total number of matching net/interconnection list.

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Cont..

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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work Conclusions References
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Overview of review 1(phase 2)

Creating the data base of all net list of bench mark. Creating an array and Adjustment of proper array length to store the net list data base. Developing the clustering algorithm combinational benchmark circuit. code for standard

Adjustment of nested loops and its length(which is a vital part to reduce time complexity and to get faster execution time). Simulation of five standard benchmark and comparison of simulation results with standard clustering algorithm by Rajaraman-Wong.
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Simulation result of C17

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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work Conclusions References
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Simulation results
The clustering algorithm has been simulated for five standard benchmark circuit. Those are c432 27 channel interrupt controller. c499 32 bit single error correcting circuit. c880 8 bit ALU. c1355 32 bit single error correcting circuit. c1908 16 bit error detector/corrector.

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Simulation Results
Example network Number Of Nodes After Clustering Number Of clusters Execution Time In Proposed method(seco nd) 1.057 1.315 3.777 17.1 33.599 Execution Time in RajaramanWong method(seco nd 1.5 2.0 4.0 20.7 37.1

C432 C499 C880 C1355 C1908

196 243 443 587 913

50 25 50 66 119

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Simulation Results

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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work Conclusions References
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Scheduling algorithm
This algorithm is used to schedule all the cluster for reducing simultaneous switching. Two scheduling algorithm has been used here. 1. ASAP(as soon as possible) 2. ALAP(as late as possible) This two algorithm will also help to find the critical path and to schedule the critical path because possibility of simultaneous switching is more there. By reducing simultaneous switching, we can reduce peak power.

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Cont..

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ASAP Value For Node 1

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ALAP Value For Node 1

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Cont.

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ASAP Value For Node 3

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SIMULTANEOUS SWITCHING PROBLEM

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SOLUTION

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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work Conclusions References
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Remaining work

After scheduling, the re-clustering algorithm has to be performed based on delay slack.

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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work conclusions References
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Conclusion
The

implementation of this technique will help to manufacture power efficient integrated circuits.

As the power is reducing, we can incorporate more applications in an integrated circuit.

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Contents
Objective Clustering algorithm

Benchmark C17
Overview of phase 1 Overview of review 1(phase 2) Simulation Results Scheduling algorithm Remaining work Conclusions References
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References
[1] Ransford Hyman, Jr., Member, IEEE, Nagarajan Ranganathan, Fellow, IEEE, Thomas Bingel, and Deanne Tran Vo,A clock control strategy for peak power and RMS current reduction using path clustering,IEEE Trans.Very Large Scale Integr.(VLSI) Syst. Pp.1-11,2012 [2] Rajmohan Rajaraman and D. F. Wong, Optimum clustering for delay minimization, IEEE Trans. on Comput.-Aided Des. Integr. Circuits, vol. 14 no. 12, December 1995. [3] Y. R. Lin, C. T. Hwang, and A. C. H. Wu, Scheduling techniques for variable voltage low power design, ACM Trans. Design Autom. Electron. Syst., vol. 2, no. 2, pp. 8197, Apr. 1997.

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THANK YOU

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