Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room-Temperature Operation

INTRODUCTION

THE heterogeneous 3-D integration and functional integration nano electronic devices. which are limited by increased power dissipation and thermal heating due to continuous scaling. Therefore, in this research, we have set down an organized design methodology for hybrid SET-CMOS circuits with a complete set of electrical and physical parameters for the 22-nm technology node at room temperature.

WHAT IS S-ET ? ( SINGLE ELECTRON TRANSISTOR)

The most fundamental 3-terminal single electron device are called SET
SET has one which as coulomb blockade (CB) island

PRINCIPLE OPERATION

It relies on single electron tunneling through a nano scale junction

The electron tunnels are transferred 1 by 1 through the channel

SET CIRCUIT

COULOMB BLOCKADE EFFECTS

Coulomb blockade or single-electron charging effect, which allows for the precise control small number of electrons It reduces the number off electrons in a switching transition
Which reduces power dissipation Raising the higher level off circuit integration

DESIGN CONSIDERATIONS FOR A SET LOGIC (INVERTER)

The relations between the electrical and physical parameters that must be satisfied for its implementation are as follows i) The charging energy EC = e2/2C. ii) The operating temperature T e2/(2kBC). iii) The voltage level e/C. iv) The device maximum operating frequency 1/(RtC) but when CL > C, CL affects the frequency. v) The SET inverting voltage gain is given by AV = Cg/Cj nevertheless, it is also a function of temperature.

SET inverter circuit

Design Parameters

VS = Vi high" = VO high" = 800 mV Vi low" = VO low" = 0 V,

gain = 1, T = 300 K,

Rt = 1 M.
Derived parameters: Cj = 0.03 aF, Cg = 0.045 aF, Cb = 0.05 aF (all within the fabrication capability).

SET inverter transient analysis.

SET Parameters

VS = Vi high" = 800 mV
Vi low" = 0 V gain = 1, T = 300 K

Rt = 1 M

Cj = 0.03 aF
Cg = 0.045 aF and Cb = 0.05aF

HYBRID SET-CMOS INTEGRATED LOGIC DESIGN AND SIMULATION

the SET is fabricated on the pre-metal dielectric (PMD) of a CMOS-IC which is useful to minimize the interconnect delay. where a SET-inverter drives a 22-nm CMOS inverter with interconnect parasitics The SET inverter

Hybrid SET-CMOS cascaded inverter with interconnects parasitic. (a) Model (b) Circuit diagram

Hybrid SET-CMOS - parasitic simulation

COMPARISON BETWEEN SET AND CMOS LOGIC

Parameters CMOS cascaded inverter SET casded inverter

Total power -3dB bandwidth

delay

130nW 81 GHz
7.8 ps

4nW 210 GHz

3.1 ps

CONCLUSION

We present a simulation method in the CADENCE environment capable of simulating very large-scale hybrid SETCMOS circuits efficiently. The simulation results for SET and hybrid SET-CMOS logic are based on analytically derived SET parameters that are within the fabrication range for devices operational at room temperature and that take into account the interconnect parasitics at the 22-nm node. We successfully designed and simulated a SETCMOS interface capable of efficiently driving a CMOS logic with interconnect, for a stable high output voltage of 800 mV and a bandwidth of approximately 1.1 GHz. The bandwidth and, hence, the delay can be improved with design tradeoffs and by connecting SETs in parallel.