VHDL

VHDL:
VHSIC Hardware description language VHSIC: Very High Speed Integrated Circuit

Features of VHDL:
The U.S department of Defense (DoD) and IEEE developed a highly capable HDL with the following features. * Designs may be decomposed hierarchically * Each design has a both well defined interface ( for connecting it to other elements)and a precise behavioral specification ( for simulating it) * Behavioral specification may use either algorithm or an actual hardware structure to define an elements operation. * Concurrency , timing , and clocking can all be modeled. VHDL handles asynchronous as well as synchronous circuit structures. * The logical operation and timing behavior of a design can be simulated.

DESIGN FLOW
There are several steps in a VHDL based design process often called as Design Flow. These steps are applicable to any HDL based design process. The steps are,

Hierarchy/ Block diagram

Coding

Compilation

Simulation/ Verification

Synthesis

Fitting/ Place + Route

Timing verification

VHDL Program Structure:

VHDL was designed with principles of structured programming in mind, borrowing ideas from the pascal and Ada software programming languages, The key idea is, Defining the interface of a hardware module while hiding its internal details

Program structure of VHDL consists two parts *VHDL entity * VHDL Architecture An entity is simply a declaration of modules Input and outputs

Entity Declaration

An architecture is a detailed description of the modules internal structure or behavior

Architecture Definition

VHDL Entities and Architectures:

Entity Wrapper concept
Architecture

Entity A
Architecture A

Entity B
Architecture B

Entity C
Architecture C

Entity D
Architecture D

Entity E Hierarchical use

Architecture E

Entity F
Architecture F

Characteristics of VHDL: Some of the characteristics of VHDL are. Comment lines start with two hyphens(--) and end at the end of the line Space and line breaks are ignored VHDL defines many special character strings called Reserved words or key words Ex: Entity, port, is, in, out, end etc. User defined identifiers begin with a letter and contain letters, digits and underscores. Reserved words and identifiers are not case sensitive Every statement ends with a semicolon.

Syntax for entity declaration:

The main purpose of entity declaration is to define its external interface signals or ports in its port declaration part. Entity entity-name is port ( signal-names : mode signal-type; signal-names : mode signal-type; ........... signal-names : mode signal-type); End entity-name; It consists of , Entity-name: A user selected identifier to name the entity. Signal-names : A comma separated list of one or more user defined identifiers to name external interface signals. Mode : One of four reserved words specifying the signal direction. in : Signal is input to the entity out : signal is output to the entity Buffer : The signal is output to the entity and also its value can be read inside the entitys architecture inout : The signal can be used as input and output of the entity Signal-type: A built in or user defined signal type.

Syntax for Architecture definition:

The main purpose of architecture definition is to define entitys internal operation. The syntax is as follows, Architecture architecture-name of entity-name is type declarations signal declarations constant declarations Function definitions procedure definitions component declarations Begin Concurrent statement Concurrent statement .. Concurrent statement End Architecture-name;

Signal declaration:
This signal declaration gives the same information about a signal as in a port declaration except mode is not specified. Signal signal-name : signal-type; signal defined using this declaration refers to the names of the wires used in the logic diagram.

Variable declaration:
Variables are same as signals except they dont have physical significance in the circuit . Variables are normally used in VHDL functions, procedures , process etc. Variable variable-name : variable-type;

Types and constants:

All the signals, variables, constants used in the VHDL should have some associated type. The type specifies the set or range of values that a object can take on.
VHDL Predefined types are:

bit, character, Severity_level, integer, string, boolean, real, time, Bit_vector.

Integer is defined as the range of integers including at least the range (-2^31+1 to 2^31-1) Boolean has two values true and false Character type contains all the characters in the ISO 8-bit character set. The first 128 are ASCII characters. The various integer and boolean operators are +, - , * , / , mod , rem , abs , * * ,Integer operators and, or, nand , nor, xor ,xnor , not Boolean operators

The most commonly used types in VHDL are User defined types and enumerated types. Enumerated types are the types whose values are specified by listing their values.

Ex: Character, Boolean

Syntax for types and constant declarations:

-- type type-name is (value-list); Ex: type traffic-light-state is (reset, stop, wait, go); -- subtype subtype-name is type-name start to end; Ex: subtype twoval_logic is std-logic range 0 to 1; subtype negint is integer range -2^31+1 to -1; -- subtype subtype-name is type-name start down to end; Ex: subtype bitnum is integer range 31 down to 0; -- constant constant-name : type-name:=value; Ex: constant pi : integer :=abs(3.14); constant bus_size : integer :=32;

VHDL also defines an important category of user defined types called as Array types. VHDL defines an array as an ordered set of elements of the same type, where each element is selected by an array index.

SYNTAX FOR VHDL ARRAY DECLATRATIONS:

--type

type-name is array (start to end ) of element-type;

Ex: type monthly-count is array (1 to 12) of integer ; -- type type-name is array (start down to end ) of element-type; Ex: type input is array (7 down to 0) of std_logic; -- type type-name is array (range-type) of element-type; Ex: type lightstate is array (traffic-light-state ) of integer; -- type type-name is array (range-type start to end) of element-type; -- type type-name is array (range-type start down to end) of elementtype;

Ex:
--type STD_ULOGIC is (u, x, 0, 1, z, w, L,H,-); subtype std_logic is resolved std-ulogic ;

ARRAY LITERALS: EX: B<=(1, 1, 1, 1); W:=(0=>1,8=>1.) B<=111111 ARRAYSLICE: Ex:M(6 to 9); bus size(31 down to 5); Concatenation operator: Ex: 0&1&1&z=> 011z B( 6 down to 0) & B(7)=>B(7 down to 0)

Functions and Procedures:

Like in a high level language, in VHDL also a function accepts a number of arguments and returns a result. Each of the argument and the result in a VHDL function or a function call have a predetermined type.
Syntax For Function Definition: Function function-name (signal-name : signal-type; signal-name : signal-type; .. signal-name : signal-type) return return-type is type declarations variable declarations constant declarations function definitions procedure definitions begin sequential-statement . sequential-statement end function-name;

Procedures:

A VHDL procedure is similar to a function except it does not return any result. A function call can be used in the place of an expression, a procedure call can be used in place of an statement. A procedure allow their arguments to be specified with type out or inout.

LIBRARIES AND PACKAGES:

Library:
A VHDL library is a place where the VHDL compiler stores information about a particular design project, including intermediate files that are used in the analysis, simulation and synthesis of the design. For a VHDL design, The compiler automatically creates and uses a library named work. Each project has its own work library, but it must also refer to a common library containing shared definitions. The designer specifies the name of such a library using LIBRARY clause at the beginning of the design file. Ex: library IEEE; Specifying the name of the library in the design gives it access to any previously analyzed entities and the architectures but will not allow access to type definitions.

Packages:
Specifying the name of the library in the design gives it access to any previously analyzed entities and the architectures but will not allow access to type definitions. Accessing of type definitions is possible using packages with use clause. A VHDL package is a file containing definitions of objects that can be used in other programs. Objects that can be put into packages are signal, type , constant, function, procedures, and component declarations. Designer can use a package in the design by including a use clause at the beginning of the design file.

Ex : use ieee . Std_logic_1164. all;

use ieee . Std_logic_arith. all; use ieee . Std_logic_signed. all; use ieee . Std_logic_unsigned. all;

Syntax for user defined package:

package package-name is type declarations signal declarations variable declarations constant declarations component declarations function definitions procedure definitions End package-name; package body package-name is type declarations constant declarations function definitions procedure definitions End package-name;

Architecture design methodologies: Executable portion of a VHDL design i.e, architecture can be modeled in different ways. different models are specified based on way of using concurrent and sequential executable statements. Based on this, the different design models of architecture are. --Structural design model --Data flow design model -- Behavior design model -- Mixed design model (often used)

Structural design elements:

A VHDL architecture that uses components is often called a structural description or structural design, because it defines the precise interconnection structure of signals and entities that realizes the entity.

Component statement:
Syntax for component instantiation: ---label: component-name port map (signal1, signal2, signal(n-1), signaln); ---label: component-name port map (port1=>signal1, port2=>signal2, port(n-1)=>signal(n-1), port n=>signal n); Syntax for component declaration: component component-name port ( signal-names : mode signal-type; signal-names : mode signal-type; ........... signal-names : mode signal-type); End component;

Generate statement:
Generate statement is used in the design, if the design consists multiple copies of a particular structure with in the an architecture. Generate statement allows the creation of repetitive structures using a kind for loop, with out having to write out all of the component instantiations individually. Syntax for VHDL for-generate statement: label: for identifier in range generate concurrent statement End generate;

EX: Program to perform inversion of a bus.

library ieee; use ieee.std-logic_1164. all; Entity inv8 is port (x: in std_logic_vector(1 to 8); y: out std_logic_vector(1 to 8)); End inv8; Architecture inv8 of inv8 is Component inv is port (a: in std_logic ;b: out std_logic); End component; Begin g1:for k in 1 to 8 generate U1:inv port map (x (k), y (k)); End generate; End inv8;

Generic constant: Syntax:

Entity entity-name is Generic (constant-name : constant-type; constant-name : constant-type; . constant-name : constant-type); port ( signal-names : mode signal-type; signal-names : mode signal-type; ........... signal-names : mode signal-type); End entity-name;

Ex: program illustrating generic constant declaration.

library ieee; use ieee.std-logic_1164. all; Entity geninv is generic (width : positive) port (x: in std_logic_vector(Width-1 down to 0); y: out std_logic_vector(width-1 down to 0)); End geninv; Architecture geninv of geninv is Component inv is port (a: in std_logic ;b: out std_logic); End component; Begin g1:for k in width-1 down to 0 generate U1:inv port map (x (k), y (k)); End generate; End geninv;

Ex: program illustrating generic map

library ieee; use ieee.std-logic_1164. all; Entity businv is port (x8: in std_logic_vector(7 down to 0); y8: out std_logic_vector(7 down to 0); x16: in std_logic_vector(15 down to 0); y16: out std_logic_vector(15 down to 0); x32: in std_logic_vector(31 down to 0); y32: out std_logic_vector(31 down to 0)); End businv; Architecture businv of businv is Component geninv is generic (width : positive) port (x: in std_logic_vector(Width-1 down to 0); y: out std_logic_vector(width-1 down to 0)); End component; Begin u1: geninv generic map (width=>8) port map(x8, y8); u2: geninv generic map (width=>16) port map(x16, y16); u3: geninv generic map (width=>32) port map(x32, y32); End businv;

Dataflow Design Elements: If concurrent statements allow VHDL to describe a circuit in terms of the flow of data and operations on it within the circuit,then this style is called a dataflow description or dataflow design. Two additional concurrent statements use in dataflow designs are, Concurrent signal assignment statements: -- signal_name<=expression; --signal_name<= expres., when boolean-expres., else expres.,when boolean-expres., else ------------expres.,when boolean-expres., else expression;

Selected signal assignment statement: This statement evaluates the given expression and when matches with one of the choices,it assigns the corresponding signal-value to signal-name. The choices in each when clause may be a single value of expression or a list of values seperated by vertical bars(|). The keyword others can be used in the last when clause to denote all values of expression that have not yet been covered. syntax: with expression select signal-name<=signal-value when choices, signal-value when choices, ------signal-value when choices;

Ex: Illustrating the usage of select signal statement library ieee; use ieee.std_logic_1164. all; Entity 4:1mux is port (x: in std_logic_vector(0 to 3); s: in std_logic_vector(1 down to 0); y: out std_logic); End 4:1mux; Architecture 4:1mux of 4:1mux is Begin with s select y<=x(0) when 00, x(1) when 01, x(2) when 10, x(3) when 11, x when others; End 4:1mux;

BEHAVIORAL DESIGN ELEMENTS: The key benefit of any hardware description language is its ability to create a behavioral design or behavioral description. VHDLs key behavioral element is process. process is a collection of sequential statements that executes in parallel with other concurrent statements or other process. A process statement can be used anywhere that a concurrent statement can be used. Using the process we can specify a complex interaction of signals and events in a way that executes in essentially zero simulated time during simulation and that gives rise to synthesized combinational or sequential circuit5 that performs the modelled operation directly.

Syntax of a VHDL Process statement: process (signal-name, signal-name.. ..signal-name) type declarations variable declarations constant declarations function definitions procedure definitions begin sequential-statement ----------sequential-statement End process;

Sensitivity list: The list of signals in the process definition is called sensitivity list, determines when the process runs. A VHDL process is always running or suspended. when any signal in its sensitivity list changes its value, the process starts execution, starting with its first sequential statement and continuing untill the end. If any signal in the sensitivity list changes value as a result of running the process, it runs again. This process continues untill no signal changes its value.

--Sequential signal assignment: signal-name <= expression; --Variable signal assignment: variable-name := expression; --IF statement: * if Boolean-expression then sequential-statement end if; * if Boolean-expression then sequential-statement else sequential-statement end if; * if Boolean-expression then sequential-statement elsif Boolean-expression then sequential-statement . elsif Boolean-expression then sequential-statement end if; * if Boolean-expression then sequential-statement elsif Boolean-expression then sequential-statement . elsif Boolean-expression then sequential-statement else Boolean-expression end if;

Case statement: When we need to select among multiple alternatives based on the value of just one signal or expression, a case statement is usually more readable and may yield a better synthesized circuit.

syntax: case expression is when choices=>sequential-statement; ---------when choices =>sequential-statement; end case;

Ex: Illustrating the usage of case statement

library ieee; use ieee.std_logic_1164. all; Entity 4:1mux is port (x: in std_logic_vector(0 to 3); s: in std_logic_vector(1 down to 0); y: out std_logic); End 4:1mux; Architecture 4:1mux of 4:1mux is Begin Process(s) begin case s is when 00=> y<=x(0); when 01=> y<=x(1); when 10=> y<=x(2); when 11=> y<=x(3); when others=>x; End case; End process; End 4:1mux;

LOOP STATEMENT: syntax: loop sequential-statement; ----------------sequential-statement; end loop; FOR LOOP: for identifier in range loop sequntial-statement; --------------sequential-statemnt; End loop;

WHILE LOOP: While boolean-expression loop sequential-statement; --------------sequential-statemnt; end loop; AFTER STATEMENT: WAIT STATEMENT: