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Built-In Self-Test(BIST)
By GSV.PRABHUJI ROLLNO:13
OVERVIEW
BIST (Built-In Self-Test) BIST Architecture
BIST Advantages
BIST Disadvantages & Applications Conclusion
Testing a Circuit
Response Analyzer
+
Test Engineer
Computers
Self-Test a Circuit
Response Analyzer
BIST is a design technique in which some parts of the circuit are used for testing the circuit itself.
Embedded Tester Core 1 Test Controller Test access BIST mechanism Core 2
BIST
Core 3
Core 4
Core 5
Source: Elcoteq
BIST Architecture
Key Elements of BIST Test pattern Generator (TPG) Output Response Analyzers (ORA) Circuit Under Test (CUT) A Distribution system for transmitting data from TPG to CUT and from CUT to ORAs. A BIST Controller
Pseudo-Random testing
Weighted test generator Adaptive Test Generator
Pseudo-Exhaustive testing
Constant Weight Counter Combined LFSR and Shift Register Combined LFSR and XOR Cyclic LFSR
Exhaustive Testing
Apply all possible 2^n test patterns to a n input circuit. A binary counter can be used. Or a maximum length autonomous LFSR can be used( add special circuit to generate all zeros). Normally applied when number of inputs are less than 25.
Pseudorandom Testing
Patterns are generated deterministically but have characteristics of random patterns. Pseudo-random patterns without replacement can be generated using autonomous LFSRs. Test length can be chosen to achieve the desired fault coverage. This can be determined using fault simulation.
Pseudo-exhaustive Testing
Circuit is segmented & each segment is tested exhaustively, by Logical Segmentation, Cone Segmentation, Sensitized path segmentation, Physical Segmentation.
Segments the circuit into parts and each segment is exhaustively tested.
Response compression : A process to form a signature from complete output responses. Signature : Compressed form of saved test results. Alias : Errorous output when faulty & fault-free sig. are the same.
Fault Tolerant : Producing copies of CUT and conclude the correct signature by finding the subset which generates the same signature.
Ones count : The no. of times when 1 occurs in each output (counter). Transition count : The no. of transitions(0 =>1,1=>0) in the output (XOR +counter).
Parity checking : The parity of response string, 0 if even & 1 if odd
(XOR + D-FF).
Syndrome checking : The normalized no. of 1s in output string (k/2**n
when k is no. of minterms in an n input circuit), (All possible combination tests). LFSR : Shift register that feed back bits through XOR functions. Used both for Pseudo-Random Binary Sequence (PRBS) generation and for signature generation.
Advantages
Single stuck-at faults Delay faults Single stuck-at faults in BIST hardware
Disadvantages
Silicon area overhead Access time Requires the use of extra pins Correctness is not assured
Applications
Mission-critical sytems. self-diagnostic circuitry (consumer electronics).
CONCLUSION
Based upon the Test Generation and Response Compression of BIST the following varitions will results.
Testing time
Memory cost
QUESTION TIME
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