1

Low-Noise Amplifier
2
RF Receiver
BPF1 BPF2 LNA
LO
Mixer BPF3 IF Amp
Demodulator
Antenna
RF front end
3
Low-Noise Amplifier
First gain stage in receiver
Amplify weak signal
Significant impact on noise performance
Dominate input-referred noise of front end


Impedance matching
Efficient power transfer
Better noise performance
Stable circuit
LNA
subsequent
LNA frontend
G
NF
NF NF
1
+ =
4
LNA Design Consideration
Noise performance
Power transfer
Impedance matching
Power consumption
Bandwidth
Stability
Linearity
5
Noise Figure
Definition


As a function of device


G: Power gain of the device
out out
in in
out
in
N S
N S
SNR
SNR
NF = =
source
source device
N G
N G N
NF

+
=
6
NF of Cascaded Stages

Overall NF dominated by NF
1

[1] F. Friis, Noise Figure of Radio Receivers,
Proc. IRE, Vol. 32, pp.419-422, July 1944.
S
in
/N
in
G
1
, N
1
,
NF
1
G
i
, N
i
,
NF
i
G
K
, N
K
,
NF
K
S
out
/N
out
1 2 1 2 1
3
1
2
1
1 1 1
1 1

+ +

+ =
K
K
...G G G
NF
...
G G
NF
G
NF
NF NF
7
Simple Model of Noise in MOSFET
f WLC
k
f V
ox
g
= ) (
2
Flicker noise
Dominant at low frequency
Thermal noise
: empirical constant
2/3 for long channel
much larger for short channel
PMOS has less thermal noise

Input-inferred noise
m d
g kT f I 4 ) (
2
=
V
g
I
d
V
i
f WLC
k
g
kT f V
ox m
i
+ =

4 ) (
2
8
Noise Approximation
Thermal noise
1/f noise
Band of interest
Frequency
Noise spectral
density
Thermal noise
dominant
9
Power Transfer and Impedance Matching
L
L L s s
s
del
R
jX R jX R
V
P
2
+ + +
=
s
s s
X X R R
L
R
V V
P P
L s L s
4
*
0 ,
max
= =
= + =
Power delivered to load


Maxim available power

R
s
V
s
jX
s
jX
L
R
L
I

V

Impedance matching
Load and source impedances conjugate pair
Real part matched to 50 ohm
10
Available Power
Equal power on load
and source resistors
11
Reflection Coefficient
*
* *
max
4
) )( (
4
aa
R
IZ V IZ V
R
V V
P
s
s s
s
s s
=
+ +
= =
s
s
R
IZ V
a
2
+
=
*
* * *
max
4
) )( (
bb
R
Z I V IZ V
P P P
s
s s
del ref
=

= =
R
s
V
s
jX
s
jX
L
R
L
I

V

s
s
R
IZ V
b
2
*

=
s L
s L
Z Z
Z Z
a
b
+

= = I
*
2
) (
* *
L L
del
Z Z I I
P
+
=
L
IZ V =
12
Reflection Coefficient
No reflection
Maximum power transfer
13
S-Parameters
Parameters for two-port system analysis
Suitable for distributive elements
Inputs and outputs expressed in powers
Transmission coefficients
Reflection coefficients
14
S-Parameters
2 22 1 21 2
2 12 1 11 1
a S a S b
a S a S b
+ =
+ =
a
1
b
1
b
2
a
2
S
11
S
12
S
22
S
21
15
S-Parameters
S
11
input reflection coefficient with
the output matched

S
21
forward transmission gain or
loss

S
12
reverse transmission or
isolation

S
22
output reflection coefficient with
the input matched
0 1
2
2
22
0 1
2
1
12
0 2
1
2
21
0 2
1
1
11
=
=
=
=
=
=
=
=
a
a
a
a
a
b
S
a
b
S
a
b
S
a
b
S
16
S-Parameters
S Z
1
Z
2
V
s1
V
s2
I
1
V
1
I
2
V
2
0
2 2 2
*
2 2 2
22
0
1
2
2 2 2
*
1 1 1
12
0
2
1
1 1 1
*
2 2 2
21
0
1 1 1
*
1 1 1
11
1
1
2
2
) Re(
) Re(
) Re(
) Re(
=
=
=
=
+

=
+

=
+

=
+

=
s
s
s
s
V
V
V
V
Z I V
Z I V
S
Z
Z
Z I V
Z I V
S
Z
Z
Z I V
Z I V
S
Z I V
Z I V
S
17
Stability Condition
Necessary condition


where
Stable iff

where
1
| | 2
| | | | | | 1
21 12
2 2
11
2
22
>
A +
=
S S
S S
K
S
21 12 22 11
S S S S
S
= A
1 | |
2
> + A L L
S
2
| | | |
| |
2
22
2
11
21 12
S S
S S L
+
+ =
18
A First LNA Example
Assume
No flicker noise
r
o
= infinity

C
gd
= 0
Reasonable for appropriate
bandwidth
Effective transconductance
R
s
V
s
V
s
R
s
4kTR
s
V
gs
g
m
V
gs
4kTg
m
in s
in m
s
o
meff
Z R
Z g
V
i
G
+

= =
i
o
19
Power Gain
Voltage input
Current output
2
2 2
2
2 2
2
2
*
*
1
) ( 1
1 ) ( 1
) ( 1
| |
|
|
.
|

\
|
~
+
=
+
=
+

=
+

= = =
s
T
gs s
m
gs s
m
gs s
gs m
in s
in m
meff
s s
o o
R C R
g
C R j
g
C j R
C j g
Z R
Z g
G
V V
i i
G
e
e
e
e e
e
20
Noise Figure Calculation
Power ratio @ output
Device noise + input-induced noise
Input-induced noise
2
2
2 2 2
2 2
2
) / (
1
) 1 ( 1
) ( 1
4
4
1
gs m
m s
m s
gs s
m s
gs s
m
s
m
in
in device
C g
g R
g R
C R
g R
C R
g
kTR
g kT
N G
N G N
NF
e

+ + =
+ + =
+
+ =

+
=
gs
m
T
C
g
= e
21
Unity Current Gain Frequency

Device
i
out

i
in

( )
( )
( )
( )
1

= =
=
=
T in
T out
i
in
out
i
i
i
A
i
i
A
T
e e
e
e
0dB
f
T
A
i
f
frequency
22
Small-Signal Model of MOSFET
C
gs

C
gd

r
ds

C
db

R
g
: Gate resistance
r
i
: Channel charging
resistance
V
gs
g
m
V
gs
C
gd
i
1
i
2
r
i
C
gs
i
1
i
2
C
db
r
ds
R
g
V
1
V
2
V
1
V
2
23
e
T
Calculation

gd gs i g gs i g gd gs
gd gs i gd gs
V
C C r R s C sr R C C s
C C r s C C s
V
I
Y
2
2
0
1
1
11
) ( 1
) (
2
+ + + +
+ +
= =
=
V
gs
g
m
V
gs
C
gd
i
1
i
2
r
i
C
gs
C
db
r
ds
R
g
V
1
V
gs
g
m
V
gs
C
gd
i
1
i
2
r
i
C
gs
R
g
V
1
gd gs i g gs i g gd gs
gd gs i gd gs i m
V
C C r R s C sr R C C s
C C r s sC C sr g
V
I
Y
2
2
0
1
2
21
) ( 1
) 1 (
2
+ + + +
+
= =
=
24
e
T
of NMOS and PMOS
0.25um CMOS Process
*
[2] Tajinder Manku, Microwave CMOS - Device Physics and Design,
IEEE J. Solid-State Circuits, vol. 34, pp. 277 - 285, March 1999.
( )
m
gd gs
m
T
g
C C
g

+
~ e
1
) (
) (
21
11
=
T
T
j Y
j Y
e
e
Set:
Solve for e
T
25
Noise Performance


Low frequency
R
s
g
m
>> ~ 1
g
m
>> 1/50 @ R
s
= 50 ohm
Power consuming
CMOS technology
g
m
/I
D
lower than other tech
e
T
lower than other tech
2
2
1
T
m s
m s
g R
g R
NF
e
e

+ + =
26
Review of First Example
No impedance matching
Capacitive input impedance
Output not matched
Power transfer
S
11
=(1-sRC
gs
)/(1+sRC
gs
)
S
21
=2Rg
m
/(1+sRC
gs
), R=R
s
=R
L
Power consumption
High power for NF
High power for S
21
27
Impedance Matching for LNA
Resistive termination
Series-shunt feedback
Common-gate connection
Inductor degeneration
28
Resistive Termination
2
/ 1 / 1
gs I s
m
C j R R
g
G
e + +
=
Current-current power gain


Noise figure
R
s

V
s
I
s
R
s
4kT/R
s
V
gs
g
m
V
gs
i
o
R
I
R
I
4kT/R
I
4kTg
m
2
2
2
1 1
1
T
s m
I s m
s
I
s
R g
R R g
R
R
R
NF
e
e

+
|
|
.
|

\
|
+ + + =
29
Comparison with Previous Example
Previous example


Resistive-termination
2
2
2
1 1
T
s m
I
s
s m I
s
R g
R
R
R g R
R
NF
e
e

+
|
|
.
|

\
|
+ + + =
2
2
1
T
m s
m s
g R
g R
NF
e
e

+ + =
Introduced by input
resistance
Signal attenuated
30
Summary - Resistive Termination
Noise performance
Low-frequency approximation
Input matched R
s
= R
I
= R


Broadband input match
Attenuate signal
Introduce noise due to R
I
NF > 3 dB (best case)
R g
NF
m
4
2 + >
31
Series-Shunt Feedback
Broadband matching






Could be noisy
R
s

V
s
R
a

R
F

R
L

V
gs
g
m
V
gs
R
F
i
out
R
a
C
gs
R
s
V
s
R
L

gs L F a a L m
gs a a m L F
in
C R R R s R R g
C sR R g R R
R
) ( ) ( 1
) 1 )( (
+ + + + +
+ + +
=
) )( ( 1
) (
) )( ( 1
) )( 1 (
a s gs m
s a F s F a gs
a s gs m
s F a m
out
R R sC g
R R R R R R sC
R R sC g
R R R g
R
+ + +
+ +
+
+ + +
+ +
=
32
Common-Gate Structure
R
s

R
L

V
s
R
s
4kTR
s
V
gs
g
m
V
gs
R
L

4kTg
m
V
s
R
s
4kTR
s
V
gs g
m
V
gs
R
L

4kTg
m
g
m
gs s s m
m
s
out
eff
C sR R g
g
V
I
G
+ +

=
=
1
33
Input Impedance of CG Structure
Input impedance
Y
in
=g
m
+sC
gs

Input-impedance matching
Low frequency approximation
Direct without passive components
1/g
m
=R
s
=50 ohm
34
Noise Performance of CG Structure
| |
2
2
2 2 2 2
2 2 2
2
4 1
) 1 ( 1
) ( ) 1 (
4
4
1
T
gs s s m
m s
gs s s m
m
s
m
in
in device
C R R g
g R
C R R g
g
kTR
g kT
N G
N G N
NF
e
e

e

+ + =
+ + + =
+ +
+ =

+
=
2 2 2
2
2
) ( ) 1 (
gs s s m
m
eff
C R R g
g
G G
e + +
= =
Signal attenuated
35
Power Transfer of CG Structure
R
s
= R
L
= R = 50 ohm








S
11
=0, S
21
=1 @ Low frequency
gs s
gs s
gs s s m
gs s s m
s in
s in
C sR
C sR
C sR R g
C sR R g
Z Z
Z Z
S
+

=
+ +

=
+

=
2
1
1
*
11
gs
gs s s m
m L
eff L
sC
C sR R g
g R
G R S
+
=
+ +
= =
2
2
1
2
2
21
36
Summary CG Structure
Noise performance
No extra resistive noise source
Independent of power consumption
Impedance matching
Broadband input matching
No passive components
Power consumption
g
m
=1/50
Power transfer
Independent of power consumption
37
Inductor Degeneration Structure
R
s

V
s
L
s

L
g

V
gs
g
m
V
gs
i
out
C
gs
R
s
V
s
L
g

L
s

Z
in
V
in
i
in
(
(

+ + + =
+ + + =
+ + + =
gs
s m
gs
s g in
s
gs
in m in
gs
in g in
s gs m in
gs
in g in in
C
L g
sC
L L s I
sL
sC
I g I
sC
I sL I
sL V g I
sC
I sL I V
1
) (
)
1
(
1
) (
1
Z
in
38
Input Matching for ID Structure
Z
in
=R
s

IM{Z
in
}=0

RE{Z
in
}=R
s
gs
s m
gs
s g in
C
L g
sC
L L s Z + + + =
1
) (
gs s g
C L L ) (
1
2
0
+
= e
s
gs
s m
R
C
L g
=
V
gs
g
m
V
gs
i
out
C
gs
R
s
V
s
L
g
L
s

Z
in
g
m
L
s
/C
gs
39
Effective Transconductance
V
gs
g
m
V
gs
i
out
C
gs
R
s
V
s
L
g
L
s

Z
in
g
m
L
s
/C
gs
) ( ) ( 1
) (
2
s g gs s m gs s
m
in s
gs m
s
out
eff
L L C s L g C R s
g
Z R
sC g
V
I
G
+ + + +
=
+
= =
40
Noise Factor of ID Structure
Calculate NF at e
0
2 2
2 2
2
) ( 1
) (
4
4
1
0
s m gs s
m s
s m gs s
m
s
m
in
in device
L g C R
g R
L g C R
g
kTR
g kT
N G
N G N
NF
+ + =
+
+ =

+
=
~
e

e e
2 2 2 2
2
2
) ( )] ( 1 [
s m gs s s g gs
m
eff
L g C R L L C
g
G G
+ + +
= =
e e
= 0 @ e
0
41
Input Quality Factor of ID Structure
CR R I I
C I I
power Lost
power Stored
Q
e
e 1
*
*
= =
=
C
gs
R
s
V
s
L
g
L
s

g
m
L
s
/C
gs
C

R

V

L
gs s s m gs s
gs s m s gs
in
C R L g C R
C L g R C CR
Q
e e
e e
2
1
) (
1
) / (
1 1
=
+
=
+
= =
I
42
Noise Factor of ID Structure
2
2 2
1
1
) ( 1
0
in m s
s m gs s
m s
Q g R
L g C R
g R
NF

e e
+ =
+ + =
~
) (
1
s m gs s
in
L g C R
Q
+
=
e
Increase power transfer
g
m
L
s
/C
gs
= R
s

Decrease NF
g
m
L
s
/C
gs
= 0

Conflict between
Power transfer
Noise performance
43
Further Discussion on NF
s g
s
s g gs m s
s m
s m gs s
m s
L L
L
L L C g R
L g
L g C R
g R
NF
+
+ =
+
+ =
+ + =
~

e e
4
1
) (
1 ) ( 4
1
) ( 1
2
2 2
0
Frequency @ e
0

e
2
~= 1/C
gs
/(L
g
+L
s
)
Input impedance
matched to R
s
R
s
C
gs
=g
m
L
s

Suitable for hand
calculation and design
Large L
g
and small L
s
T s s
R L e =
gs g s
C L L
2
0
1 e = +
44
Power Transfer of ID Structure
R
s
= R
L
= R = 50 ohm






@

) ( ) ( 1
) ( 1
) ( 1
) ( 1
2
2
2
2
*
11
s g gs gs s s m
s g gs
gs s s m s g gs
gs s s m s g gs
s in
s in
L L C s C R L g s
L L C s
C sR L sg L L C s
C sR L sg L L C s
Z Z
Z Z
S
+ + + +
+ +
=
+ + + +
+ + +
=
+

=
) ( ) ( 1
2
2
2
21
s g gs s m gs s
L m
L eff
L L C s L g C R s
R g
R G S
+ + + +
= =
) (
1
s m gs s
in
L g C R
Q
+
=
e gs s g
C L L ) (
1
2
0
+
= e
s
L T
in L m
s m gs s
L m
R
R
j Q R g j
L g C R j
R g
S S
0 0
21 11
2
) (
2
; 0
e
e
e
= =
+
= =
45
Computing A
v
without S-Para
R
s

V
s
L
s

L
g

) (
2 / 1
2 2
; 2
: match imput and resonance At
0
0 0
0
o o s
T
s
o
v
s T s s gs s m o
gs in m gs m o s s in
s in
Y Y R
j
V
V
A
R jV R C j V g I
C j I g V g I R V I
R Z
+
= =
= =
= = =
=
e
e
e e e
e
46
Power Consumption
DD T gs
ox
DD D
V V V
L
W C
V I P
2
) (
2
= =

WL C C
ox gs
3
2
=
) (
T gs ox m
V V
L
W
C g =
( )
2
2 2
2
3
T gs ox
gs
m
V V
L
W
C
C
L g
=

gs
s m
s
C
L g
R =
s
gs s
m
L
C R
g =
) / 1 ( 3
1
) ( 3
1
3
) ( 3 3 3
3 2
0
2 2 2
2
0
2 2
2
0
2
2 2
2
2 2 2 2
s g s
DD s
s g
DD T
DD gs
T
s g
DD
s
s
DD gs
s
s
DD
gs
m
L L L
V R L
L L
V L
V C
L
P
L L
V
L
R L
V C
L
R L
V
C
L g
P
+
=
+
|
|
.
|

\
|
= =
+
= = =
e e
e

e
e
47
Power Consumption
) / 1 (
1
3 2
0
2 2
s g s
s
L L L
R L
P
+

e
Technology constant
L: minimum feature size
: mobility, avoid mobility saturation region
Standard specification
R
s
: source impedance
e
0
: carrier frequency

Circuit parameter
L
g
, L
s
: gate and source degeneration inductance

s g
s
L L
L
NF
+
+ =
~

e e
4
1
0
48
Summary of ID Structure
Noise performance
No resistive noise source
Large L
g
Impedance matching
Matched at carrier frequency
Applicable to wideband application, S
11
<-10dB

Power transfer
Narrowband
Increase with g
m
Power consumption
Large L
g
49
Cascode
Isolation to improve S
12

@ high frequency

Small range at V
d1

Reduced feedback effect
of C
gd

Improve noise
performance

R
s

V
s
L
s

L
g

V
bias
L
L

M
2
M
1
V
d1
V
o
50
R
s

V
s
L
s

L
g

L
L

M
1
V
o
V
gs
g
m
V
gs
C
gs
R
s
V
s
L
g

L
s

L
L

V
o
51
LNA Design Example (1)
R
s

V
s
L
s

L
g

L
d

M
2
M
1
L
vdd

V
bias
M
4
L
b1
C
b1
T
m
C
m
M
3
L
gnd

L
out

Input
bias
Off-chip
matching
[3] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier, IEEE J. Solid-
State Circuits, vol. 32, pp. 745 759, May 1997.
L
b2
C
b2
V
out
Output
bias
V
dd
52
LNA Design Example (1)
R
s

V
s
L
s

L
g

L
d

M
2
M
1
L
vdd

V
bias
M
4
L
b1
C
b1
T
m
C
m
M
3
L
gnd

L
out

[3] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier, IEEE J. Solid-
State Circuits, vol. 32, pp. 745 759, May 1997.
Unwanted
parasitics
Supply
filtering
53
Circuit Details
Two-stage cascoded structure in 0.6 m
First stage
W
1
= 403 m determined from NF
L
s
accurate value, bondwire inductance

L
d
= 7nH, resonating with cap at drain of M
2
Second
4.6 dB gain
W
3
= 200 m

54
55
LNA Design Example (2)
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996.
C
s

M
2
M
1
M
3
Off-chip
matching
N
s
R
B

V
RF
C
B

I
REF

I
B1

V
B1
M
4
M
5
M
7
M
6
V
out1
R
X
C
X
N
L
Off-chip
matching
NF = 1 + K/g
m
g
m
= g
m1
+ g
m2
56
Simplified view
57
LNA Design Example (2)
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996.
C
s

M
2
M
1
M
3
Bias
feedback
N
s
R
B

V
RF
C
B

I
REF

I
B1

V
B1
M
4
M
5
M
7
M
6
V
out1
R
X
C
X
N
L
M
8
58
LNA Design Example (2)
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996.
C
s

M
2
M
1
M
3
Bias
feedback
N
s
R
B

V
RF
C
B

I
REF

I
B1

V
B1
M
4
M
5
M
7
M
6
V
out1
R
X
C
X
N
L
M
8
59
LNA Design Example (2)
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996.
C
s

M
2
M
1
M
3
Bias
feedback
N
s
R
B

V
RF
C
B

I
REF

I
B1

V
B1
M
4
M
5
M
7
M
6
V
out1
R
X
C
X
N
L
M
8
V
A

DC output = V
B1
60
61
LNA Design Example (3)
Objective is to design tunable RF LNA that
would:

Operate over very wide frequency range with very fine
selectivity
Achieve a good noise performance

Have a good linearity performance

Consume minimum power
62
LNA Architecture
The cascode architecture
provides a good input
output isolation
Transistor M
2
isolates the
Miller capacitance
Input Impedance is obtained
using the source
degeneration inductor Ls
Gate inductor L
g
sets the
resonant frequency
The tuning granularity is
achieved by the output
matching network
V
DD

L
S

L
G

M
1

M
2

L
D

R
2

R
1

M
3

Output to
Mixer
Input to LNA
Matching
Network
63
Matching Network
The output matching tuning
network is composed of a
varactor and an inductor.
The LC network is used to
convert the load impedance
into the input impedance of
the subsequent stage.
A well designed matching
network allows for a
maximum power transfer to
the load.
By varying the DC voltage
applied to the varactor, the
output frequency is tuned to
a different frequency.

64
Simulation Results - S11
The input return loss
S11 is less than 10dB
at a frequency range
between 1.4 GHz and
2GHz
Input return loss
65
Simulation results - NF
The noise figure is 1.8
dB at 1.4 GHz and rises
to 3.4 dB at 2 GHz.
Noise Figure
66
Simulation Results - S22
S22 at 1.7725 GHz S22 at 1.77 GHz
By controlling the voltage applied to the varactor the output frequency
is tuned by 2.5 MHz.
The output return loss at 1.77 GHz is 44.73 dB and the output return
loss at 1.7725 GHz 45.69 dB.
67
Simulation Results - S22
S22 at 1.9975 GHz
S22 at 2 GHz
The output return loss at 2 GHz is 26.47 dB and the output return
loss at 1.9975 GHz 26.6 dB.
68
Simulation Results - S21
The overall gain of
the LNA is 12 dB
S21 at 1.4025 GHz
69
Simulation Results - Linearity
-1dB compression point
IIP3
The third order input intercept is 3.16 dBm
-1 dB compression point ( the output level at which the actual gain
departs from the theoretical gain) is 12 dBm
70
From an earlier slide:
f WLC
k
f V
ox
g
= ) (
2
Flicker noise
Dominant at low frequency
Thermal noise
: empirical constant
2/3 for long channel
much larger for short channel
PMOS has less thermal noise
Input-inferred noise
m d
g kT f I 4 ) (
2
=
V
g
I
d
V
i
f WLC
k
g
kT f V
ox m
i
+ =

4 ) (
2
Not accurate for low voltage short channel devices
71
Modifications
is called excess noise factor
= 2/3 in long channel
= 2 to 3 (or higher!) in short
channel NMOS (less in PMOS)

o

m
do d
g
kT g kT f I 4 4 ) (
2
= =
Thermonoise
72
g
do
vs g
m
in short channel
73
g
do
vs g
m
in short channel
74
Fliker noise
Traps at channel/oxide interface randomly
capture/release carriers



Parameterized by Kf and n
Provided by fab (note n 1)
Currently: Kf of PMOS << Kf of NMOS due to buried channel
To minimize: want large area (high WL)

f
K
f
K
f I
f WLC
k
f V
f
n
f
d
ox
g
~ =
~
) (
) (
2
2
75
Induced Gate Noise
Fluctuating channel potential couples
capacitively into the gate terminal, causing a
noise gate current


o is gate noise coefficient
Typically assumed to be 2
Correlated to drain noise!

2
2
5
4
|
|
.
|

\
|
=
o e
e
o
T
do ng
g kT i
76
Input impedance
Set to be real and equal to source resistance:
real
gs
m
gs
g in
C
L g
sC
L L s s Z
deg
deg
1
) ( ) ( + + + =
gs g
C L L ) (
1
deg
2
0
+
= e
s
gs
m
R
C
L g
=
deg
77
Output noise current
| | ) 1 4 ( 2 1 ) (
2 2 2
+ + = Q c g kT f I
d d do d
_ _
Noise scaling factor:
| | ) 1 4 ( 2 1
4
1
2 2
+ + Q c
d d
_ _
Where for 0.18 process
c=-j0.55, =3, o=6, g
do
=2g
m
,
_
d
= 0.32

o
_
5
do
m
d
g
g
=
s
g
gs s
R
L L
C R
Q
2
) (
2
1
deg 0
0
+
= =
e
e
78
Noise factor
Noise factor scaling coefficient:
( )
2 2
) 1 4 ( 2 1
2
d d
m
do
nf
Q c
g
g
Q
K _ _

+ +
|
|
.
|

\
|
=
( )
2 2
) 1 4 ( 2 1
2
1
d d
m
do
T
o
Q c
g
g
Q
F _ _

e
e
+ +
|
|
.
|

\
|
|
|
.
|

\
|
+ =
4
2
1 ) ( 4 1
0
2 2
0
0
Q
C R
g R N G
N G N
NF
T
gs s
m s in
in device

e
e
e

e e |
|
.
|

\
|
+ = + =

+
=
~
Compare:
79
Noise factor scaling coefficient versus Q
80
Example
Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8 GHz
From
gs s
C R
Q
0
2
1
e
=
fF
e Q R
C
s
gs
442
) 2 ( 9 8 . 1 2 ) 50 ( 2
1
2
1
0
= = =
t e
nH
e
R
g
C R
L
T
s
m
gs s
17 . 0
9 8 . 47 2
50
deg
= = = =
t e
nH L
C
L
C L L
gs
g
gs g
5 . 17
1
) (
1
deg
2
0 deg
2
0
= =
+
=
e
e
81
Have We Chosen the Correct Bias Point?
IIP3 is also a function of Q
82
If we choose Vgs=1V
I
dens
= 175 A/m
From C
gs
= 442 fF, W=274m
I
bias
= I
dens
W = 48 mA, too large!

Solution 1: lower I
dens
=> lower power,
lower f
T
, lower IIP3
Solution 2: lower W => lower power, lower
Cgs, higher Q, higher NF
83
Lower current density to 100
Need to verify that IIP3 still OK (once we know Q)
84
We now need to re-plot the Noise Factor scaling coefficient
- Also plot over a wider range of Q
Lower current density to 100
43 . 0
5
2
68 . 0
5
68 . 0
15 . 1
78 . 0
~ = = ~ ~

o
_
do
m
d
do
m
g
g
g
g
GHz 8 . 42 2
9 . 2
78 . 0
= ~ ~ t e
fF
mS
C
g
gs
m
T
( )
2 2
) 1 4 ( 2 1
2
1
1
d d
m
do
T
o
Q c
Q g
g
F _ _
e
e
+ +
|
|
.
|

\
|
|
|
.
|

\
|
+ =
85
86
Recall
We previously chose Q = 2, lets now choose Q = 6
- Cuts power dissipation by a factor of 3!
- New value of W is one third the old one
m
m
W

91
3
274
~ =
87
R
s
= 50 Ohms, Q = 6, f
o
= 1.8 GHz, f
t
=
42.8 GHz
I
bias
= I
dens
W =100A/m*91m=9.1mA
Power = 9.1 * 1.8 = 16.4 mW
Noise factor scaling coeff = 10
Noise factor = 1+ w
o
/w
t
* 10
= 1+ 1.8G/42.8G *10 = 1.42
Noise figure = 10*log(1.42) = 1.52 dB
C
gs
=442/3=147fF
L
deg
=R
s
/w
t
=0.19nH
L
g
=1/(w
o
^2C
gs
) L
de
g = 53 nH
88
Other architectures of LNAs
Add output load to achieve voltage gain
In practice, use cascode to boost gain
Added benefit of removing Cgd effect
89
Differential LNA
Value of Ldeg is now much better controlled
Much less sensitivity to noise from other circuits

But: Twice the power as the single-ended version
Requires differential input at the chip
90
LNA Employing Current Re-Use
PMOS is biased using a current mirror
NMOS current adjusted to match the PMOS current
Note: not clear how the matching network is achieving a 50 Ohm match
Perhaps parasitic bondwire inductance is degenerating the PMOS or
NMOS transistors?
91
Combining inductive
degeneration and current reuse
Current reuse to save power
Larger area due to two degeneration
inductor if implemented on chip
NF: 2dB, Power gain: 17.5dB, IIP3: -
6dBm, Id: 8mA from 2.7V power supply
Can have differential version
F. Gatta, E. Sacchi, et al, A 2-dB Noise Figure 900MHz Differential CMOS LNA,
IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452
92
At DC, M1 and M2 are in cascode
At AC, M1 and M2 are in cascade
S of M2 is AC shorted
Gm of M1 and M2 are multiplied.
Same biasing current in M1 & M2
LIANG-HUI LI AND HUEY-RU CHUANG, MICROWAVE JOURNAL from the February 2004 issue.
93
b a o
b m b
a m a m a m a
i i i
v g i
v g v g v g i
+ =
=
+ + =
3
3
3
3
2
2 1
IM3 components in the drain
current of the main transistor has
the required information of its
nonlinearity
Auxiliary circuit is used to tune the
magnitude and phase of IM3
components
Addition of main and auxiliary
transistor currents results in
negligible IM3 components at
output
Sivakumar Ganesan, Edgar Snchez-sinencio, And Jose Silva-martinez
IEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 12, December 2006
94
MOS in weak inversion has speed problem
MOS transistor in weak inversion acts like bipolar
Bipolar available in TSMC 0.18 technology (not a parasitic BJT)
Why not using that bipolar transistor to improve linearity ?
95
Inter-stage Inductor gain boost
Inter-stage inductor with
parasitic capacitance form
impedance match network between
input stage and cascoded stage
boost gain lower noise figure.
Input match condition will be
affected
96
Folded cascode
Low supply voltage

Ld reduces or eliminates
Effect of C
gd1

Good f
T


97
Design Procedure for Inductive
Source Degenerated LNA
Noise factor equations:
( )
2 2
) 1 4 ( 2 1
2
1
1
d d
m
do
T
o
Q c
Q g
g
F _ _
e
e
+ +
|
|
.
|

\
|
|
|
.
|

\
|
+ =
( )
2 2
) 1 4 ( 2 1
2
1
d d
m
do
nf
Q c
Q g
g
K _ _ + +
|
|
.
|

\
|
=
98
Targeted Specifications
Frequency 2.4 GHz ISM Band
Noise Figure 1.6 dB
IIP3 -8 dBm
Voltage gain 20 dB
Power < 10mA from 1.8V


99
Step 1: Know your process
A 0.18um CMOS Process
Process related
t
ox
= 4.1e-9 m
c = 3.9*(8.85e
-12
) F/m
= 3.274e
-2
m^2/V.s
V
th
= 0.52 V
Noise related
o = gm/gdo
o/ ~ 2
~ 3
c = -j0.55
100
Step 2: Obtain design guide plots
101
Insights:
g
do
increases all the way with current
density I
den
g
m
saturates when I
den
larger than
120A/m
Velocity saturation, mobility degradation ----
short channel effects
Low gm/current efficiency
High linearity
o deviates from long channel value (1)
with large I
den

102
Obtain design guide plots
103
Insights:
f
T
increases with V
od
when V
od
is small and
saturates after V
od
> 0.3V --- short channel
effects
C
gs
/W increases slowly after V
od
> 0.2V
f
T
begins to degrade when V
od
> 0.8V
g
m
saturates
C
gs
increases

Should keep V
od
~0.2 to 0.4 V
104
Obtain design guide plots
3-D plot for visual
inspection
2-D plots for
design reference
k
nf
vs input Q and current density
105
Design trade-offs
For fixed I
den
, increasing Q will reduce the
size of transistor thus reduce total power --
-- noise figure will become larger
For fixed Q, reducing I
den
will reduce
power, but will increase noise factor
For large I
den
, there is an optimal Q for
minimum noise factor, but power may be
too high

106
Obtain design guide plots
Linearity plots :IIP3 vs. gate overdrive and transistor size
107
Insights:
MOS transistor IIP3 only, when embedded into
actual circuit:
Input Q will degrade IIP3
Non-linear memory effect will degrade IIP3
Output non-linearity will degrade IIP3
IIP3 is a very weak function of device size
Generally, large overdrive means large IIP3
But the relationship between IIP3 and gate overdrive
is not monotonic
There is a local maxima around 0.1V overdrive

108
Step 4: Estimate f
T


Small current budget ( < 10mA )
does not allow large gate over drive :
V
od
~ 0.2 V ~ 0.4 V
f
T
~ 40 ~ 44 GHz
109
Step 4: Determine I
den
, Q and
Calculate Device Size
Select I
den
= 70 A/m, =>V
od
~0.23V
Gm/W~0.4
110
If Q = 4, IIP3 will have enough margin:
Estimated IIP3:
IIP3(from curve) 20log(Q) = 8-12 = -4dBm
Specs require: -8 dBm
111
Q=4 and I
den
= 70A/m meet the
noise factor requirement
112
Gm=0.4*128 ~ 50 mS
f
T
= gm/(Cgs*2pi) = 48 GHz
113
Step 6: Simulation Verification
Large deviation
114
115
Comparison between targeted
specs and simulation results
Parameter Target Simulated
Noise Figure 1.6 dB 0.8 dB
Drain Current < 10mA 8 mA
Voltage gain 20 dB 21 dB
IIP3 -8 dBm -6.4 dBm
P1dB -20dbm
S11 -17 dB
Power supply 1.8 V 1.8 V