TIMER/COUNTER : USED AS A COUNTER

TIMER/COUNTER : USED AS A TIMER

MAIN COMPONENTS OF A TIMER/COUNTER MODULE

Source: This could either be a synchronous clock provided by an oscillator or an event that is not so periodic such as a pushbutton connected to the Timerx Clock Input pin (TxCKI).

Introduction Timer 0
Timer 0 is an 8-bit Timer/Counter module 8-bit prescaler (shared with WDT). Selectable internal or external clock source. Interrupt on overflow (2550). Source edge selection (positive or negative going edge). To configure the Timer0 module the OPTION_REG a Special Function Register (SFR) is used.

SIMPLIFIED DIAGRAM OF TIMER 0 MODULE

SIMPLIFIED DIAGRAM OF TIMER 0 MODULE

Timer 0 operation
The bits of OPTION_REG used to control timer 0 operation are as shown below (Available at Address 0x81 Bank 1).
Bit7 Bit6 Bit5 Bit4 Bit3 PSA Bit2 PS2 Bit1 PS1 Bit0 PS0

RBPU INTEDG T0CS T0SE Selecting the Timer0 Source

T0CS: Timer0 Clock Source Select bit. If TOCS = 1 : Signal present on T0CKI (Timer0 Clock Input) pin used as Timer0 source If TOCS = 0 : Internal instruction cycle clock used as source.
- Internal instruction cycle = (Microcontroller oscillator

Frequency)/4

SOURCE EDGE SELECTION (For EXTERNAL SOURCE ONLY)

T0SE: Timer0 Source Edge Select bit. If T0SE = 1 : TMR0 register increments on high-to-low transition on T0CKI pin If T0SE = 0 : TMR0 register increments on low-to-high transition on T0CKI pin This bit is XORd with the logic level on the T0CKI pin.

Bit 7

Bit 4

Bit 0

PRESCALER ASSIGNMENT AND CONFIGURATION

To assign the prescaler to Timer0, the Prescaler assignment bit needs to be cleared (0). PSA: Prescaler Assignment bit If PSA = 1 : Prescaler is assigned to the Watchdog Timer module If PSA = 0 : Prescaler is assigned to Timer0 module

PRESCALER ASSIGNMENT

PRESCALER RATE SELECTION

The Timer0 Interrupt

The Timer0 module has an 8-bit register for the counts, the TMR0 register located in BANK0 and BANK2. It can count up to 255. If the TMR0 value is 255 (0xFF) and it is increased once more, then the TMR0 register will become 0 (0x00) and the TMR0 interrupt shall be raised. The TMR0IE interrupt can be controlled by the INTCON register bit 5 (TMR0IE - TMR0 Interrupt Enable). When the TMR0 Interrupt is raised, the INTCON bit 2 (TMR0IF - TMR0 Interrupt Flag) is raised to indicate that the TMR0 interrupt is occurred. The TMR0IF must be cleared in software (BCF INTCON,TMR0IF) for the TMR0 interrupt to be re-enabled.

Bit 6 - INTEDG: RB0/INT pin Interrupt Edge Select

This bit is Readable and Writable and after a reset it will get the value 1. By altering this bit, you can select the RB0/INT pin pulse edge that the RB0/INT interrupt will occur. The values it can get are: 0: The RB0/INT interrupt will occur on the falling edge of the RB0/INT pin 1: The RB0/INT interrupt will occur on the rising edge of the RB0/INT pin

Bit7

Bit6
INTEDG

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

TIMER1
The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>). Timer1 can operate in one of two modes: As a Timer As a Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).

Timer 1
In Timer mode, Timer1 increments at every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit, TMR1ON (T1CON<0>). Timer1 also has an internal Reset input. This Reset can be generated by either of the two CCP modules.

When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored and these pins read as 0.

TIMER1 BLOCK DIAGRAM

T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

bit 7-6 Unimplemented: Read as 0 bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits PS1, PS0 Timer1 rate
00 1:1

01 1:2 10 1:4 11 1:8 bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)

T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit. When TMR1CS =1 T1SYNC =1 Do not synchronize external clock input T1SYNC = 0 Synchronize external clock input When TMR1CS = 0: T1SYNC bit is ignored. Timer1 uses the internal clock. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge). Timer1 works as Counter. 0 = Internal clock (FOSC/4). Works as Timer. bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1

Timer1 Operation in Timer / Counter Mode

Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect since the internal clock is always in sync. Counter mode: Timer1 may operate either in a Synchronous, or an asynchronous mode, depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment.

TIMER2
Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable and is cleared on any device Reset. The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset.

TIMER2 BLOCK DIAGRAM

T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

TOUTPS3: Timer2 post TOUTPS0 scaler rate 0000 1:1 0001 1:2 0010 1:3 . . 1111 1:16 bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off

T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits T2CKPS1: Timer2 pre T2CKPS0 scaler rate 00 1 01 4 1X 16

Working of Timer 2
The prescaler and postscaler counters are cleared when any of the following occurs: - a write to the TMR2 register - a write to the T2CON register - any device Reset (POR, MCLR Reset, WDT Reset or BOR) TMR2 is not cleared when T2CON is written. The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate the shift clock.

 Clock freq=1MHz Time-1uS, Delay-1ms 1uS *4* (255-N) = 1mS => N = 05 to be entered in TMR0 register No:of counts-1000 255*x = 1000 => x= 3.9 or 4 =>1:4 prescaling

Initializing Internal clock source Timer0

Initializing External clock source Timer0

Initializing Internal clock source Timer1

Initializing External clock source Timer1-Synchronous mode

Initializing External clock source Timer1-Asynchronous mode

Initializing Timer2

ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) Converter module has eight Inputs. The conversion of an analog input signal results in a corresponding 10-bit digital number. The A/D module has high and low-voltage reference input that is software selectable to some combination of VDD, VSS, RA2 or RA3. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D clock must be derived from the A/Ds internal RC oscillator.

A/D BLOCK DIAGRAM

The A/D module has four registers

A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL)

A/D Control Register 0 (ADCON0)

A/D Control Register 1 (ADCON1)

ADCON0 REGISTER (ADDRESS 1Fh)

bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits

Bits of ADCON0 Register (Address 1Fh)

bit 5-3 CHS2:CHS0: Analog Channel Select bits CHS2:CHS0 000 001 Analog Channel Select bits
Channel 0 (AN0) Channel 1 (AN1)

010 011 100 101 110 111

Channel 2 (AN2)
Channel 3 (AN3) Channel 4 (AN4) Channel 5 (AN5) Channel 6 (AN6) Channel 7 (AN7)

Bits of ADCON0 Register (Address 1Fh)

bit 2 GO/DONE: A/D Conversion Status bit - When ADON = 1: GO/DONE =1 A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared by hardware when the A/D conversion is complete) GO/DONE = 0 A/D conversion not in progress bit 0 ADON: A/D On bit 1 = A/D converter module is powered up 0 = A/D converter module is shut-off and consumes no operating current

ADCON1 REGISTER (ADDRESS 9Fh)

bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as 0. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as 0.

bit 6 ADCS2: A/D Conversion Clock Select bit

bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits

A/d conversion TAD Cycles

AD result registers.