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invented & demonstrated @ Bell Labs The first IC appeared in the market in 1961
~14 years after the transistorFlip-flop: 2 transistors & resistorsCost
~$100
The Silicon Technology is Growing... Now on the same amount of Silica ~500 times faster operations 10 million transistors, 1/2 mile of interconnectCost few cents!!! The Technology changes compared to the IC Design cycle
Moores Law
In 1965, GardonMoore stated that the silicon technology will double the number of transistors on a chip every 2 years!!!
And it is happening !!!!!!
Many applications 1968 :Noyce, Moore & Grove Forms Intel !!SemiconductorMemory Chip
Microprocessor Technology
Microprocessor = IC Tech +SoftwareProcessor
Power+Memory capacity
Software market
Advantages of VLSI ?
Less AREA (compactness at system levels) Less POWERConsumption Less TESTING(more complex testing) Higher RELIABILITY
(due to improved on-chip interconnects) Higher SPEED(due to reduced interconnect length) Significant COST SAVINGS
Design Approaches
Custom
full control of design
EPLA/EPLD -FPGA
Electrically Programmable (in the Field)
Implemented in
To compress the digital world. To explore the hidden perfection and create the brain of a machine.
*The above two are considered as a very difficult tasks in the field of electronics engineering, where in fact its a very simple technology.
Goal:
Most reliable design process, with minimum cost
There
Interfaces (PORTS)
Behavior
Structure Test Benches Simulation Synthesis
Dataflow
Behavioral
Structural Kind of BORING sounding huh?? Well, it gets more exciting with the details !! :)
this assigns the Boolean signal x to the value of Boolean signal y... i.e. x = y this will occur whenever y changes....
Entity declaration
(Describes the input/output ports of a module)
entity name port names port mode (direction)
entity reg4 is port ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end entity reg4;
punctuation
reserved words
port type
Architecture body
Describes an implementation of an entity May be several per entity
Behavioral architecture
Describes the algorithm performed by the module Contains Process statements, each containing
Sequential statements, including
Signal assignment statements and Wait statements
Omit entity at end of entity declaration. Omit architecture at end of architecture body.
entity reg4 is port ( d0, d1, d2 : in bit d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end reg4;
architecture behav of reg4 is begin process (d0, ... ) ... begin ... end process ; end behav;
Structural architecture
implements the module as a composition of
subsystems contains
signal declarations, for internal interconnections
the entity ports are also treated as signals
component instances
instances of previously declared entity/architecture pairs
multiplier
multiplicand
shift_reg
control_ section
shift_ adder
reg
product
Either using simulator. Or with a process that verifies correct operation Or logic analyzer.
signals
Specified in wait statements. Resumes and schedules new values on output
signals.
Schedules transactions. Event on a signal if value changes.
Logic Optimization
Technology Mapping Placement Routing Programming Unit
structural coding styles. Distinguish coding for synthesis versus coding for simulation. Use scalar and composite data types to represent information. Use concurrent and sequential control structure to regulate information flow. Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures).
Executable specification. Functionality separated from implementation. Simulate early and fast (Manage complexity) Explore design alternatives. Get feedback (Produce better designs) Automatic synthesis and test generation (ATPG for ASICs) Increase productivity (Shorten time-to-market) Technology and tool independence. Portable design data (Protect investment)
Hardware Design.
IC designing. ASIC Development.
THANK YOU
E-Mail Gaurav_rai@live.com