VLSI DESIGN STYLES

VLSI Design Styles

Full Custom Design

Semi Custom Design

Programmable

Standard Cell based Design

Gate Array based Design

Programmable Logic Devices(PLA,CPLD etc)

FPGA

Channel less Gate Array

Channeled Gate Array

Structured Gate Array

FIELD PROGRAMMABLE GATE ARRAY(FPGA)

Contain thousands or more no. of logic gate with programmable interconnect Fast prototyping and cost effective chip design options specially for low volume application Not suitable for very high speed operations

FPGA ARCHITECTURE
Typical FPGA Chip consists of: i) Logic modules or configurable logic block(CLB) ii) Input output block/buffer iii) Programmable Interconnects Programming of interconnects performed by programming RAM cells whose o/p connected to the gate of CMOS switch

FPGA ARCHITECTURE

General Architecture of XILINX FPGA

FPGA ARCHITECTURE

Detailed view of switch matrices & Interconnection routing between CLBs

FPGA MANUFACTURERS
SRAM based FPGA: ALTERA (Example: CYCLONE-II) Development tools: Quartus-II XILINX (Example: SPARTAN-III) Development tools: Xilinx ISE Anti-fuse based FPGA: ACTEL(one time programmable)

FULL CUSTOM IC DESIGN

All Logic cells and mask layers are customized. It allows designers to include analog circuits, memory cells or mechanical structure on an IC. Full custom Ics are most expensive to manufacture and to design. Manufacturing time is typically eight weeks

FULL CUSTOM IC DESIGN FLOW

FULL CUSTOM DESIGN FLOW

Steps: Design Entry(Using Schematic Editor or HDL) Logic Synthesis(Synthesis tools to create a netlist ,a description of logic cells & their connection) System partitioning(Divide a large system into smaller parts) Pre-layout simulation(check the design is correct or not)

FULL CUSTOM DESIGN FLOW

Floor planning(Arrange the block of net list on the chip) Placement (Decide the location of cells in a block) Routing(Interconnection between blocks) Parasitic Extraction Post Layout Simulation

STANDARD CELL BASED DESIGN

Predesigned logic cells (AND,OR,MUX,Flip Flops) are available inside standard cell library. Mega functions , full custom blocks are available inside library. Chip designer defines only the placement of cells and the interconnect Every transistor in standard cell can be chosen for max. speed & min area

STANDARD CELL BASED DESIGN

Disadvantages: Buying standard cell library Time needed to fabricate all layers

GATE ARRAY BASED DESIGN

Each logic cell in gate array library uses fixed size transistor known as base cell Transistors are isolated from one array to another by using oxide layer or by using transistor that is permanently off.

Fig-> Gate array based D flip flop module.

Thank you