CPLD AND FPGA ARCHITECTURE AND APPLICATIONS

UNIT-I

Some Important Events

1947 1958 1962 1970 1970 1970 1971 1978 1984 Shockley, et al. the first transistor at Bell Labs Jack Kilby the first integrated circuit; Hofstein, et al. (MOSFET); Intel the first 1024-bit DRAM; Fairchild the first 256-bit SRAM; Ron Cline (Signetics) the first PLD (PLA); Intel the first microprocessor, 4004; Monolithic Memories Inc. the first PAL; Altera the first CPLD based on a combination of CMOS and EPROM technologies; Xilinx - the first FPGA, the XC2064 - a radical new form of programmable logic;

1985

Programmable Logic

Programmable Logic Devices (PLDs) are ICs with a large number of gates and flip flops that can be configured with basic software to perform a specific logic function or perform the logic for a complex circuit. Major types of PLDs are:

SPLD: (Simple PLDs) are the earliest type of array logic used for fixed functions and smaller circuits with a limited number of gates. (The PAL and GAL are both SPLDs).
CPLD: (Complex PLDs) are multiple SPLDs arrays and interconnection arrays on a single chip. FPLD: (Field Programmable Gate Array) are a more flexible arrangement than CPLDs, with much larger capacity.

PLD SPLD CPLD

Some others

PROM

PLA

PAL

Main types of SPLDs

PLA-Programmable Logic Array PAL-Programmable Array Logic GAL-Generic Array Logic ROM-Read Only Memory

PLD as a Black Box

Inputs

(logic variables)

Logic gates and programmable switches

(logic functions)

Outputs

 Programmable Logic Array (PLA)

Use to implement circuits in SOP form The connections in the AND plane are programmable The connections in the OR plane are programmable
x1 x2 xn

Input buffers and inverters

x1 x1 xn xn

P1
AND plane OR plane Pk

f1

fm

 Schematic of a PLA
x1 x2 x3

f1 = x1x2+x1x3'+x1'x2'x3 f2 = x1x2+x1'x2'x3+x1x3

OR plane P1

P2

P3

P4

x marks the connections left in place after programming

AND plane f1 f2

Limitations of PLAs PLAs come in various sizes

Typical size is 16 inputs, 32 product terms, 8 outputs
Each AND gate has large fan-in this limits the number of inputs that can be provided in a PLA 16 inputs 316 = possible input combinations; only 32 permitted (since 32 AND gates) in a typical PLA 32 AND terms permitted large fan-in for OR gates as well This makes PLAs slower and slightly more expensive than some alternatives to be discussed shortly

8 outputs could have shared minterms, but not required

 Programmable Array Logic (PAL)

Also used to implement circuits in SOP form The connections in the AND plane are programmable The connections in the OR plane are NOT programmable
x1 x2 xn

Input buffers and inverters

x1 x1 xn xn

fixed connections

P1
AND plane OR plane Pk

f1

fm

PALs and GALs All PLDs contain arrays. Two important SPLDs are PALs (Programmable Array Logic) and GALs (Generic Array Logic). A typical array consists of a matrix of conductors connected in rows and columns to AND gates.

PALs have a one time programmable (OTP) array, in which fuses are permanently blown, creating the product terms in an AND array.

Simplified AND-OR array

PALs and GALs PALs are programmed with a specialized programmer that blows selected internal fuse links. After blowing the fuses, the array represents the Boolean logic expression for the desired circuit.
A A B B

What function is represented by the array? X = AB + AB The function represents an XOR gate.

PALs and GALs The GAL (Generic Array Logic) is similar to a PAL but can be reprogrammed. For this reason, they are useful for new product development (prototyping) and for training purposes.
A A B B

GALs were developed by Lattice Semiconductor. They are high speed, extremely fast devices and can interface with both 3.3 V or 5 V logic signals.

PALs and GALs PALs and GALs can be represented with a simplified diagram. A single line can represent multiple gate inputs. The logic shown is for the XOR gate, given previously.
Input buffer
A A B B

Single line with slash indicating multiple AND gate inputs

Fuse blown

X
Fuse intact

AB AB + AB

X 2
AB

Summary
PALs and GALs PALs and GALs have large array logic and include output logic that varies in complexity. The output logic is connected to each OR gate and together is referred to as a macrocell. Two types of PAL/GAL macrocells are shown. For these particular macrocells, the I/O pins can serve as an input or an output.

Tristate control

From AND array To AND array

I/O

From AND array To AND array Programmable fuse link to control output polarity

I/O

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Generic Array Logic (GAL)

An innovation of the PAL was the generic array logic device, or GAL, invented by Lattice Semiconductor Inc. This device has the same logical properties as the PAL but can be erased and reprogrammed. The GAL is very useful in the prototyping stage of a design, when any bugs in the logic can be corrected by reprogramming. GALs are programmed and reprogrammed using a PAL programmer.

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, ABHINAV PRASAD GUPTA Upper Saddle River, NJ 07458. All Rights Reserved

The OR gates

GAL16V8
(review seq_1.ppt)

Each output is programmable as combinational or registered Also has programmable output polarity And Plane

XOR gates to make inverting or non-inverting buffer

Floyd, Digital Fundamentals, 10th ed 2009 Pearson Education, ABHINAV PRASAD GUPTA Upper Saddle River, NJ 07458. All Rights Reserved

Summary
PALs and GALs The PAL16V8 is a typical SPLD. There are 16 pins that can be used as inputs and 8 pins that can be used as outputs. I/O pins are counted as both inputs and outputs.
I1 I2 I3
7 Macrocell 7 Macrocell

O1 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 O2

7 Macrocell

I4
7

I5
Programmable AND array

Macrocell

I6 I7 I8

7 Macrocell

7 Macrocell

7 Macrocell

I9 PLCC Package I/O10

7 Macrocell

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary
CPLDs

A complex programmable logic device (CPLD) has multiple logic array blocks (LABs) that are actually SPLDs on a single IC. LABs are connected via a programmable interconnect array (PIA). Various CPLDs have different structures for these elements. The PIA is the interconnection between the LABs. Logic is fitted to the CPLD and routing is determined by a high-level programming language called a hardware description language (HDL).

I/O

Logic array block (LAB) SPLD

Logic array block (LAB) SPLD

I/O

PIA I/O Logic array block (LAB) SPLD Logic array block (LAB) SPLD I/O

I/O

Logic array block (LAB) SPLD

Logic array block (LAB) SPLD

I/O

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

 Structure of a CPLD
I/O block
I/O block

PAL-like block

PAL-like block

Interconnection wires

I/O block

I/O block

PAL-like block

PAL-like block

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary
CPLDs

The architecture of a CPLD is the way in which the internal elements are configured. A portion of the Altera MAX 7000 series is shown. This structure is typical for CPLDs although densities, size, speed, and internal factors (macrocells, etc) will vary between manufacturers.
General-purpose inputs

I/O pins

I/O control block

Logic array block (LAB A) Macrocell 1

PIA

Logic array block (LAB B) Macrocell 1

I/O control block

I/O pins

816

Macrocell 2

36

36

Macrocell 2

8-16

16 Macrocell 16 8-16

16 Macrocell 16 8-16

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary
CPLDs

Macrocells in the Altera MAX 7000 series can generate up to five product terms. For expressions requiring more terms, the output can be expanded as described in the text.
Parallel expanders from other macrocells

Product-term selection matrix

Associated logic

To I/O control block

Expander example
Shared expander
A B C ABC(E + F)=ABCE + ABCF

36 lines from PIA

15 expander product terms from other macrocells

E +F

EF

Product term from another macrocell in same LAB

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary
Macrocells In addition to combination logic, some macrocells have registered outputs available (using programmable flip-flops). This allows the CPLD to perform sequential logic.
Global Global clear clock

Parallel expanders from other macrocells

MUX 5

From I/O To I/O

MUX 1 Productterm selection matrix

PRE D/T Q

C MUX 2 EN CLR

VCC Shared expander

MUX 3

MUX 4 36 lines from PIA 15 expander product terms from other macrocells

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Who makes the CPLDs?

Manufacturer CPLD Products MAX 5000, 7000 & 9000 ATF & ATV FLASH370, Ultra37000 ispLSI 1000 to 8000 XPLA MACH 1 to 5 XC9500 Lets takes a look at this URL www.altera.com www.atmel.com www.cypress.com www.latticesemi.com www.philips.com www.vantis.com www.xilinx.com

Altera
Altmel Cypress Lattice Philips Vantis Xilinx

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

The Xilinx 9500-series CPLD

The internal PLDs are called Configurable Functional Blocks (FBs or CFBs) Each FB has 36 inputs and 18 Macrocells (effectively a 36V18) Each CLPD is packaged in a plastic-leaded chip carrier (PLCC) The number of I/O pins are much less than the total number of Macrocells in family of devices

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Xinlinx CPLDs

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Architecture of Xilinx 9500-family CPLD

36 Signal pins

18 outputs

Global Clock Global set/reset Global Floyd, Digital Fundamentals, 10th ed 18 Output enable signals

3 state control 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Architecture of Xilinx FB

Most CLPDs have fewer AND terms per macrocell XC9500 has 5 whereas 16V8 has 8 and 22V10 has 8-16 Buteach macrocell can use unused ANDs froms its neigboring macrocells using the product-term-allocators

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Floyd, Digital Fundamentals, 10th ed

XC9500 Product term allocator and macrocell 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

MAX II : The Lowest-Cost CPLD Ever

New Logic Architecture
1/2 the Cost 1/10 the Power 2x the Performance 4x the Density

Non-Volatile, Instant-On Supports 3.3- / 2.5- / 1.8-V Supply Voltage

Breakthrough Technology to Expand the Market

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Floyd, Digital Fundamentals, 10th ed

29

MAX II : The Lowest-Cost CPLD Ever

New Logic Architecture
1/2 the Cost 1/10 the Power 2x the Performance 4x the Density

Non-Volatile, Instant-On Supports 3.3- / 2.5- / 1.8-V Supply Voltage

Breakthrough Technology to Expand the Market

30

MAX II, special features

Real-time ISP User Flash Memory Parallel flash loader

User Flash Memory Block

JTAG Commands

Configuration Flash Memory Block

31

MAX II Device Family

Device LEs Typical Macrocells 192 440 980 1,700 User I/O Pins 80 160 212 272 Speed Grades 3, 4, 5 3, 4, 5 3, 4, 5 3, 4, 5 Fastest tpd1 (ns) 4.5 5.5 6.0 6.5 User Flash Memory (bits) 8,192 8,192 8,192 8,192

EPM240 EPM570 EPM1270 EPM2210

240 570 1,270 2,210

32

Programmable Logic Advantages to PLDs include Reduced complexity of circuit boards Lower power requirements Less board space Simpler testing procedures Higher reliability Design flexibility

CPLD Block Diagram

1 0
FF

An individual switch In a crossbar is a diamond switch

O/Ps

I/Ps Crossbar Switch

Programmable switch for interconnecting various FBs

Function block (~ PLA w/ 1 o/p that can be FFed)

MAX 7000A & MAX 3000A Family Overview

Parameter
EPM3032A

MAX 3000A
EPM7032AE EPM3064A EPM3128A EPM3256A EPM3512A

MAX 7000A
EPM7064AE EPM7128AE EPM7512AE 10,000 512 212 7.5 116 5.6 4.7

Useable Gates Macrocells Maximum User I/O Pins tPD (ns) fCNT (MHz) tSU (ns) tCO1 (ns)

600 32 34 4.5 227 2.9 3.0

1,250 64 66 4.5 222 2.8 3.1

2,500 128 96 5.0 192 3.3 3.4

5,000 256 158 7.5 127 5.2 4.8

10,000 512 208 7.5 116 5.6 4.7

600 32 36 4.5 227 2.9 3.0

1,250 64 68 4.5 222 2.8 3.1

2,500 128 100 5.0 192 3.3 3.4

5,000 256 164 5.5 172 3.9 3.5

35

EPM7256AE

MAXComplete Voltage Portfolio 7000A & MAX 3000A Family 5.0 V 3.3 V 2.5 V Overview
MAX 7000S MAX Parameter MAX 3000A 7000AE Performance Leader High Performance Feature Leader Feature Leader Wide Range of Wide Range of Package Offerings Package Offerings Industrial-Grade Useable Gates 600 1,250 2,500 5,000 10,000 600 Offerings
EPM7032AE EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A Macrocells Maximum User I/O Pins tPD (ns) fCNT (MHz) tSU (ns) tCO1 (ns) 32 34 4.5 227 2.9 3.0 64 66 4.5 222 2.8 3.1 128 96 EPM7064AE EPM7128AE EPM7512AE

Package Offerings
2,500 128 100 5.0 192 3.3 3.4 5,000 256 164 5.5 172 3.9 3.5

1,250 64 68 4.5 222 2.8 3.1

EPM7256AE

High Performance Feature Leader Wide Range of

MAX 7000B MAX 7000A

10,000 512 212 7.5 116 5.6 4.7

Price Leader 5.0 7.5& Package Feature 7.5

192 3.3 3.4

MAX 3000A 158 208

256

512

32 36 4.5 227 2.9 3.0

Subset of 127 116 MAX 7000AE

5.2 4.8 5.6 4.7

36

MAX Macrocell
Parallel Logic Expanders (from other MCs)

Global Global Clear Clock

7000 has two Global Clock

Programmable Register
Register Bypass PRn D Q ENA CLRn

ProductTerm Select Matrix

to I/O Control Block

Clear Select

VCC

36 Programmable Interconnect Signals

37

Shared Logic Expanders

Clock/ Enable to PIA Select

16 Expander Product Terms

38

Logic block i/o

Logic block i/o

I/O Mcells

Programmable interconnect matrix (PIM)

PLA

PLA

I/O Mcells

i/o

i/o
16 Mcells per Logic block

2-24 Logic blocks per device Each logic block 36 x 48 PLA

The design software hides the CPLD resources, which enables end users to work with higher level constructs and to abstract from the architectural details

1. Karen Parnell & Nick Mehta, Programmable Logic Design Quick Start Hand Book. Available at: http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf

39

Performance and Density

Memory controllers, Bus interfaces, UARTs

Counters FSMs

High speed clocking, Delay lock loops, Digital delay lines

Cell phones, Cameras, DVD players, Portable GPS, PDAs, Home networking, MP3, Printers, Prototyping boards, controllers, Graphics cards, etc.

1985

1990

1995

from 2000

1. Karen Parnell & Nick Mehta, Programmable Logic Design Quick Start Hand Book (2006). Available at: http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf

Basic Architecture (SPLD)

In In In In Out AND Array OR Array Out Out Out

Depending on the device, the above blocks may be fixed, programmable or re-programmable.
CPLD 1.40

Basic Architecture (CPLD)

PIA (Programmable Interconnect Array)

I/O

LAB (Logic Array Block)

LAB (Logic Array Block)

I/O

I/O

LAB (Logic Array Block)

LAB (Logic Array Block)

I/O

CPLD 1.41

Altera
Altera (www.altera.com) is one of the leaders in the CPLD marketplace.
Altera offers a great range of CPLDs, FPGAs and other programmable devices. Products range from the MAX series (basic CPLD) to newer products that contain embedded microprocessors.

CPLD 1.42

Manufacturers
CPLDs are manufactured by several companies including: Altera Xilinx Cypress
All utilize similar internal configurations but require proprietary software to compile and update the devices.

CPLD 1.43

CPLD
3. CPLD featured in common FPGA:i. Large number of gates available. ii. Can include complicated feedback path.

4. CPLD application:i. Address coding ii. High performance control logic iii. Complex finite state machines

ABHINAV PRASAD GUPTA

Complex PLDs
Each manufacturer has a proprietary name for its CPLD programming system. For example, Lattice calls it "in-system programming". However, these proprietary systems are beginning to give way to a standard from the Joint Test Action Group (JTAG).

ABHINAV PRASAD GUPTA

Examples of CPLDs

Examples of CPLDs and high pin count package types

ABHINAV PRASAD GUPTA

CPLD Structure and Alternate Names

A Simple PLD (or SPLD) is usually a PLA or a PAL A Complex PLD (CPLD) is an arrangement of multiple SPLD-like blocks on a single chip. Alternative names include:
enhanced PLD (EPLD) superPAL megaPAL

Types of Macrocells
There are two types of macrocells
Hard (Hardware) Soft (VHDL library)

Soft macrocells are functions comprised of primitive cells, which are placed and routed along with the rest of the chip. No cell layouts exist for the soft macrocells. Designers can configure soft macrocells at the time of instantiation.
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Hard Macrocells
Hard macrocells implement functions using custom design, usually to achieve better performance and transistor densities. The vendor tests and verifies both the hard macrocell layout and its function. Standard cells usually use hard macrocells but in some special cases gate arrays may also use them. A hard macrocell provides speed improvement over a functionally equivalent soft macrocell. Thus the hard macrocell occupies less area.
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Altera Macrocell

Mux

Pad

Interconnect To Other Macrocells

Invert Control

Memory

Output Control

Mux
Clock Control

Global Clock
ABHINAV PRASAD GUPTA

Altera Macrocell

Xilinx
Product
XC7000 Series
XC7200 Series
Each block has 9 macrocells Each macrocells includes two OR-gates Each OR-gates is input to a two-bit ALU

XC7300 Series : Enhanced version of 7200

XC9500 Series
In-system programmability

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Xilinx: XC9500 Device Family

XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1,600 2,400 3,200 4,800 6,400 Registers 36 72 108 144 216 288 t PD (ns) 5 7.5 7.5 7.5 10 10 t SU (ns) 3.5 4.5 4.5 4.5 6.0 6.0 t CO (ns) 4.0 4.5 4.5 4.5 6.0 6.0 f CNT (MHz) 100 125 125 125 111.1 111.1 f SYSTEM (MHz) 100 83.3 83.3 83.3 66.7 66.7 Note: f CNT = Operating frequency for 16-bit counters f SYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs.

ABHINAV PRASAD GUPTA

Xilinx
Architecture of Xilinx 9500 CPLDs