HSPICE

SPICE (Simulation Program with

Integrated Circuit Emphasis)


1.
2. SPICE
3.

4.
5.
6.
7.

,
,..,
,
(ADC)
(DSP)


,ADC,
,,
,,,

HSPICE
Transmission Line
Signal Intergrity

Monte Carlo

Worst Case Analysis

Photocurrent

Cell

Radiation Effects

Characterization

Circuit Cell

Incremental

Optimization

Optimization


(Optimization)
SPICE


(hierarchical design)
()
(signal integrity)

HSPICE(photocurrent effect
model)

(total ionizing dose)

p-n
(foundry service)
(lot)

HSPICE

HSPICE
SPICET
U

(Integrated)
1950
,40,
,196025
20000.18 ,,
,

(metal-oxide-silicon filed-effect
transistor,MOSFET)1930,
,,MOS,
1960N,1960,MOS


hspice


C
D
L
R
NPN NPN BJT
PNP PNP BJT
NJF N JFET
PJF P JFET
NMOS N MOSFET
PMOS P MOSFET


..val
or
Rname 1 2 val
Cname 3 4 val

Rname=val

4
Cname=val

(MOSFET)
Mname D G S B xch L=val W=val

.model xch xmos

I name 7 8 DC val

(DCAC)

Mname

or
Vname 5 6 DC val

5
v name=val

7
I name=val


....


(node)
,SPICE,
,:
1.1.2.3.4.(Hspice
)

2.
3.(0)(GND)
4.

1.PWL(piece wise linear waveform)

pwl( t1 v1 t2 v2 t3 v3 ..)

Ex: pwl (2s 1v 3s 3.5v 4s 2.5v

+ 4.5s 0.5v 6s 5v )

2.PULSE(pulse periodic waveform)

pulse( v1 v2 td tr tf pw per )

Ex: pulse ( 2v 5v 1s 1s 1s 5s 10s)

pw

td

tr

per

tf

3.SIN(sinusoidal waveform)

Sin ( v1 v2 freq )

Ex: sin ( 0v 4v 0.5k)

freq


.OP

.DC
Ex.

.DC Vx Vy Vz X
.dc vs 1v 5v 0.1v

VX. Vy
. Vz. X

.AC
.
Ex.

.AC DEC 10 X Y
.ac dec 10 1Hz 1kHz

DEC 10 1010
.X. Y


.TF

.SENS

.TRAN ()
Ex.

.tran tx tstop tstart

.tran 0.1ms

10ms

tx. Tstop
. Tstart

1ms

: 1m10m

Hspice
1
> >

HSPICE U-2003.03

>

HSPICE U-2003.03

..sp

5
Open
.sp

6
Simulate

7
Edit

8
.
Avanwaves

curver.

Hspice
.SP
*

.end

()

()
()

()

( *
)

I1=I2=2A,R1=R2=R3=R4=2,V1=7v
.op

R2
2

I1

2A

I2
2
R1

2 R3
2

2A

2 R4

3
+ V1
7V
-


.option
I1 0 1 2A
I2 1 2 2A
V1 3 0 10v
R1 1 0 2
R2 1 2 2
R3 2 3 2
R4 2 0 2
.op
.end

Edit

,
,
,

RC
.option
1
Vs 1 0 pwl(0 0 0.01ms 5v)
R1 1 2 1k
Vs=1v +C1 2 0 1uf
.tran 0.01m 6m 0.01m
.print v(1) v(2)
.end

4RC=4ms
5v

R=1K
2
C=1uf

.option
C1 1 2 15.9u
R1 2 0 5
Vs 1 0 ac 1
.ac dec 5 100 100k
.print ac vdb(2)
.end

Vs

C1 =15.9uf

R=5

Vo

.option
C1 2 0 15.9u
R1 1 2 5
Vs 1 0 ac 1
.ac dec 10 10 10k
.print ac vdb(2)
.end

Vs

R1= 5

C1 =15.9uf

Vo

.option
R1 1 2 5
C1 2 0 10u
C2 2 3 25u
R2 3 0 20
Vs 1 0 ac 1
.ac dec 10 100 10k
.print vdb(3) vp(3)
.end

Vs

R1

C1

C2

R2

Vo

1V

-50v/s


,
,.SUBCKT
Ex.

.SUBCKT

circuit name

...

.ENDS

circuit name

.subckt cc_amp

node1 ..
node1 ..

1 2 3 4

.ends cc_amp

,
Ex.

Xname

node1 ..

X1 5 6 7 8

cc_amp

circuit name


,
,,
,..,
,

1.

2.,

3.IC,


1.,

2.,,
,
, ,
3.,.inc.lib
4.,.param

5.,,
.alter


,
1.
2.()

3.
4.
(clock skew)(ground bounce)
(signal cross)(max trace
length)(line termination)
(power supply noise)
(decoupling capacitor and placement)


Input Requests

Analysis Requests

Model/Lib Selections

.circuit parameters

.dc sweep

.circuit marco def

.circuit temp

.transient

.asic vendor lib

.circuit stimulus

.ac pole zero

.memory vendor lib

.noise distortion

.processor vendor lib

.pcb & mcm vendor

Spice Execution
.circuit simulation

Result analysis
.post graphical processing

.ground bounce,crasstalk

.Line termination
.Optimzation

Fineal design
review/Modification

Hspice
1991-1995,,TSMC
UMCMOSlevel3/level6/level13,
TSMC0.6~0.8level28,
ICDRAM,level28

LEVEL28BSIM,BSIMBerkeley Short
Channel IGFET Model,
,
MOSFET
1996,BSIM3(LEVEL49)0.5
CMOS,FET,2000
0.13~0.18,BSIM4FET

MOSFET
FET,
(kp=10u Vto=1v lambda=0.01),VGS.VDS
,.DC

.option
m1 2 1 0 0 n l=0.1u w=3u
.model n nmos (kp=10u Vto=1v
lambda=0.01)
Vds 2 0 10
Vgs 1 0 4
.dc vds 0 10 10m vgs 1 5 1
.print i(m1)
VDS0V10V
.end

VGS1V5V

VGS=5v
VGS=4v

VGS=3v
VGS=2v
VGS=1v=Vt

IR=IM1=IM2

IM2 =

( W/L )2
( W/L )1

= 0.5mA x 2 = 1mA

VDS
1mA

CMOS

CMOS
CMOS
SPICE
,
0.5pf
,

,,
,
,
,

MOS
M2

M1

MOS
100uA


AM= -gm(Rd//RL) Rin
R3+Rin

WH=

1
(R1//R2//R3)[Cds+Cgd(1-k)]

20.624DB
3FH128.7Hz

VDD

MOSOP