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Introduction
The world of microprocessors and CPUs can be divided into two parts:
complex instruction set computers (CISC processors) reduced instruction set computers (RISC processors)
CISC processors have larger instruction sets that often include some particularly complex instructions. These instructions usually correspond to specific statements in high-level languages. RISC processors exclude these instructions, opting for a smaller instruction set with simpler instructions.
Overview
the rationale for RISC processors
RISC instruction sets instruction pipelines and register windows
RISC Rationale
The first microprocessors ever developed were very simple processors with very simple instruction sets. Current CISC microprocessor instruction sets may include over 300 instructions. In general, the greater the number of instructions in an instruction set, the propagation delay is within the CPU.
RISCs Features
Fixed - Length Instructions Limited Loading and Storing Instructions Access Memory Fewer Addressing Modes Instruction Pipeline Large Number of Registers
Instruction Pipeline
A pipeline is like an assembly line in which many products are being worked on simultaneously, each at a different station. In RISC processors, one instruction is executed while the following instruction is being fetched. By overlapping these operations, the CPU executes one instruction per clock cycle, even though each instruction requires three cycles to be fetched, decoded, and executed.
Optimizing Compiler
An optimizing compiler can arrange instructions to facilitate delayed loads and branches, as well as to optimally assign operands to registers. Fewer instructions make it much simpler to design an optimizing compiler for a RISC processor than for a CISC processor.
Rt, Rs 5
Rs, Rt 5
instruction pipeline
allows RISC processors to execute one instruction per clock cycle
Instruction Pipelines
An instruction pipeline is very similar to a manufacturing assembly line. An instruction pipeline processes an instruction the way the assembly line processes a product. The first stage fetches the instruction from memory. The second stage decodes the instruction and fetches any required operands.
Fetch instruction
Fetch instruction
Store result
Execute instruction
Store result
Execute instruction
1 2 3
11 12 13 14 15 16 17
-- 11 12 13 14 15 16 -- -- 11 12 13 14 15
1 2 3 4
11 12 13 14 15 16 17
-- 11 12 13 14 15 16 -- -- 11 12 13 14 15 -- -- -- 11 12 13 14
1 2 3 4 5
11 12 13 14 15 16 17
-----
11 12 13 14 -- 11 12 13 -- -- 11 12 -- -- -- 11
15 14 13 12
16 15 14 13
Pipelines Problems
One problem is memory access. Another problem is caused by branch statements.
As we noted previously, the cache must separate instructions and data to avoid memory conflicts from the different stages of the pipeline.
There is not much that the pipeline can do about this. Instead, an optimizing compiler is needed to reorder the instructions to avoid this problem.
Register Windowing
The CPU can access data in registers more quickly than data in memory, so having more registers makes more data available faster. Having more registers also helps reduce the number of memory references, particularly when calling and returning from subroutines.
Window # 3
12 13 14 15 16
First window
executing a subroutine
Window pointer register (Second Window active) 01 0 First window
12 13 14 15 16
Second window
27
47
12 13 14 15 16
Register Renaming
Most recent processors may use register renaming to add flexibility to the idea of register windowing. A processor that uses register renaming can select any registers to comprise its working register window. The CPU uses pointers to keep track of which registers are active and which physical register corresponds to each logical register.