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10.1 Digital circuit design : An overview 10.2 Design and performance analysis of the CMOS inverter 10.3 CMOS logic gate circuits 10.4 Pseudo- NMOS logic circuits
CMOS
Replaced NMOS (much lower power dissipation) Small size, ease of fabrication Channel length has decreased significantly (as short as 0.06 m or shorter) Low power dissipation than bipolar logic circuits ( can pack more) . High input impedance of MOS transistors can be used to storage charge temporarily (not in bipolar) High levels of integration for both logic (chapter 10) and memory circuits (chapter 11) . Dynamic logic to further reduce power dissipation and to increase speed performance .
Bipolar
TTL (Transistor-transistor logic) had been used for many years . ECL (Emitter Coupled Logic) : basic element is the differential BJT pair in chapter 7 . BiCMOS : combines the high speed of BJTs with low power dissipation of CMOS . GaAs : for very high speed due to the high carrier mobility . Has not demonstrated its potential commercially .
Features to be Considered
Interface circuits for different families Logic flexibility Speed Complex functions Noise immunity Temperature Power dissipation Co$t
Fig. 10.3 Definitions of propagation delays and switching times of the logic inverter
10.2 Design and performance analysis of the CMOS inverter . 10.2.1 Circuit structure
Fig. 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion .
10.3.5 Obtaining the PUN and the PDN and Vice Versa
Fig. 10.14 CMOS realization of a complex gate
Fig. 10. 17 Proper transistor sizing for a four- input NAND gate