Basics of MOS

Energy band diagrams

E
C
E
F
=E
i
E
V
E
i
E
i
Intrinsic

E
F
E
F
N-type
P-type
qo
Fn

qo
Fp

Extrinsic Energy Bands
For N-type:
i F F
E E q = o
( )
i
D
Fn
i
D
i F
kT E E
i D
n
N
kT q
n
N
kT E E
e n N n
i F
ln
ln
/
0
=
=
= =

o
For P-type:
( )
A
i
Fp
A
i
i F
kT E E
i A
N
n
kT q
N
n
kT E E
e n N p
F i
ln
ln
/
0
=
=
= =

o
MOS structure
Gate: metal or polysilicon

MOS capacitor: two-terminal MOST
Si substrate
Oxide (SiO
2
)
Metal gate (Al)
Body or substrate terminal
Gate terminal
MOS Energy Band Diagram
Work function difference between Al and Si
- depends on material used, doping, etc.

qu
M

E
C

E
i

E
Fp

E
V

qu
Si

E
C,oxide

E
Fm

oxide
bandgap
8ev
Metal
p-type Si
MOS Energy Band Diagram
E
Fp
E
V
E
C
Bands must bend for Fermi levels to line up - Part of
voltage drop occurs across oxide, rest occurs next to
O-S interface - Amount of bending is equal to work
function difference: qu
M
- qu
Si

E
i
E
Fm
qo
F qo
S
o
F
= Fermi
potential in bulk
o
S
= surface
potential
Flat-Band Voltage

Built-in potential of MOS system

Work function difference:
V
FB
= u
m
- u
Si

Apply this voltage to flatten energy bands
MOS capacitor operation
Three regions (for p substrate)
Accumulation (V
G
< 0)
Depletion (V
G
> 0 but small)
Inversion (V
G
>> 0)
p- Si substrate
V
B
= 0
V
G

Accumulation
Negative voltage on gate: attracts holes in substrate
towards oxide - Holes accumulate on Si surface -
Electrons pushed deeper into substrate
P-type Si substrate
V
G
< 0
V
B
= 0
E
Fp
E
V
E
C
E
i
E
Fm
qV
G
Depletion
Positive voltage on gate - repels holes in substrate -
Depletion region forms - Bands bend downwards
near surface
P-type Si substrate
V
G
> 0
V
B
= 0
E
Fp
E
V
E
C
E
i
E
Fm
qV
G
Depletion region
E
ox
Inversion
Increase voltage on gate, bands bend more -
Additional minority carriers (electrons) attracted
from substrate to surface- Forms inversion layer-
Surface becomes n-type
P-type Si substrate
V
G
>> 0
V
B
= 0
E
Fp
E
V
E
C
E
i
E
Fm
qV
G
Definition of Inversion
Point at which density of electrons at surface =
density of holes in bulk
Surface potential is same as o
F
, but of different sign
E
V
E
Fp
E
i
E
C
qo
F
qo
S
= -qo
F
Inversion
Depletion region depth at inversion
A
F S Si
d
qN
x
o o c
=
2
General equation:
A
F Si
d
qN
x
o c
2 = At inversion:
This is the maximum size for depletion region
MOS transistor
Add source and drain terminals to MOS capacitor
source
drain
P-substrate
N
+
N
+
NMOS
source
drain
N-substrate
P
+
P
+
PMOS
L
W
t
ox
MOS transistor operation
Simple case: V
D
= V
S
= V
B
= 0 - Operates as MOS capacitor
When V
GS
<V
T0
, depletion region forms - No carriers in
channel to connect S and D
source drain
P-substrate
V
B
= 0
V
g
< V
T0

V
d
=0 V
s
=0
depletion
region
MOS transistor operation
When V
GS
> V
T0
, inversion layer forms
Source and drain connected by conducting n-type
layer (for NMOS)
source drain
P-substrate
V
B
= 0
V
g
> V
T0

V
d
=0 V
s
=0
depletion
region
inversion
layer
Threshold voltage components
(1) Work function difference between gate &
channel (Flat-band voltage)
(2) Gate voltage to change surface potential
(3) Gate voltage to offset depletion charge
(4) Gate voltage to offset fixed charges in gate
oxide and silicon-oxide interface
Threshold voltage (1)
Work function difference V
FB
between gate and
channel

+ =
FB T
V V
0
This accounts for built-in voltage drop
Threshold voltage (2)
Now apply additional gate voltage to achieve
inversion: change surface potential by -2o
F
+ =
F FB T
V V o 2
0
Threshold voltage (3)
Depletion region charge, due to fixed acceptor
ions



F Si A B
qN Q o c 2 2
0
=
(charge/area)
To offset this charge, need voltage
Q
B0
/C
ox

where, C
ox
=c
ox
/t
ox

Threshold voltage (4)
Finally, correct for non-ideal fixed charges -
Fixed positive charged ions at boundary between
oxide and substrate. Density = N
OX
(ions/cm
2
)

Due to impurities, lattice imperfections at
interface, positive charge density Q
ox
= qN
ox
Correct with gate voltage = -Q
ox
/C
ox

ox
ox
ox
B
F FB T
C
Q
C
Q
V V =
0
0
2o
Threshold voltage formula (for NMOS):
Threshold voltage (5)
What if substrate bias V
SB
is not zero?
Depletion width W changes
Need to account for different depletion region
charge
F Si A B
qN Q o c 2 2
0
=
SB F Si A B
V qN Q + = o c 2 2 (V
SB
= 0):
(V
SB
= 0):
Threshold voltage: general





ox
ox
ox
B
F FB T
C
Q
C
Q
V V = o 2
ox
B B
T T
C
Q Q
V V
0
0

=
( )
ox
Si A
F SB F T T
C
qN
V V V
c

o o
2
2 2
0
=
+ + =
Body
effect
coefficient
+ for NMOS
- for PMOS
Threshold Voltage
NMOS PMOS
Substrate Fermi potential o
F
< 0 o
F
> 0
Depletion charge density Q
B
< 0 Q
B
> 0
Substrate bias coefficient > 0 < 0
Substrate bias voltage V
SB
> 0 V
SB
< 0
Threshold voltage
(enhancement devices)
V
T0
> 0 V
T0
< 0
Body effect
V
T0
V
SB
(V)
Threshold voltage adjustment
Threshold voltage changed by doping the channel
region with donor or acceptor ions - For NMOS,
V
T
increased by adding acceptor ions (this
increases Q
B0
) -
Density of implanted ions = N
I
[cm
-2
]
Assume all implanted impurities are ionized
ox
I
T
C
qN
V = A
0 Approximate change in V
T0
:
MOS transistor characteristics
Cutoff: V
GS
< V
t
and I
DS
~ 0
Linear: V
GS
> V
T
, V
DS
< V
GS
-V
T

Inversion layer connects drain and source. Current
is almost linear with V
DS

Saturation: V
GS
>V
T
, V
DS
>V
GS
-V
T
Channel is
pinched-off. Current saturates.
Linear mode
When V
GS
>V
T
, an inversion layer forms between
drain and source - Depth of channel depends on V
between gate and channel - Drain end narrower due
to larger drain voltage - Drain end depth reduces as
V
DS
is increased
source drain
P-substrate
V
B
= 0
V
g
> V
T0

V
d
< V
GS
-V
T0
V
s
=0
depletion
region
Channel
(inversion
layer)
Linear I/V Equation
Linear I/V Equation
Valid for a continuous channel from S to D
( ) | |
2
2
1
DS DS T GS ox n D
V V V V
L
W
C I = u
Gradual Channel Approximation:
Assume dominant electric field in y-direction
Current is constant along channel
Saturation mode
When V
DS
= V
GS
- V
T
:
No longer a voltage drop of V
T
from gate to
substrate at drain
Channel is pinched off
source drain
V
B
= 0
V
g
> V
T0

V
d
> V
GS
-V
T0

V
s
=0
depletion
region
pinch-off point
Saturation I/V Equation
If V
DS
is further increased, no increase in current -
Pinch-off point moves closer to source - Channel
between that point and drain is depleted - High
electric field in depleted region accelerates electrons
towards drain - To get saturation current, use linear
equation with V
DS
= V
GS
- V
T

( )
2
2
1
TN GS ox n D
V V
L
W
C I = u
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
I

VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Linear Saturation
V
DS
= V
GS
- V
T

V
DS

I
D
S

Ideal MOS I-V Characteristics
Channel Length Modulation
As V
DS
is increased, pinch-off point moves closer
to source - Effective channel length becomes
shorter - Current increases due to shorter channel
Summary: MOS I/V
Drain voltage V
DS

D
r
a
i
n

c
u
r
r
e
n
t

I
D
S

V
GS1

V
GS2

V
GS3

Linear
Saturation
without
channel-length
modulation
with
channel-
length
modulation
V
DS
= V
GS
-V
T