Combinational Logic

N inputs Combinational circuits M outputs

Outputs, at any time, are determined by the input combination When input changed, output changed immediately Real circuits is imperfect and have propagation delay A combinational circuit Performs logic operations that can be specified by a set of Boolean expressions Can be built hierarchically
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Timing Diagram
Describe the functionality of a logic circuit across time Represented by a waveform For combinational logic, Output is a function of inputs

Timing Diagram of an AND Gate (Output=AB)

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9

t10 t11

t12 Time

Output (No Delay)

Note that the Output change can occur at any Time for Combinational logic

Timing Diagram Example

A
Y X Z t2 t3 t4 t5 t6 t7 t8 t9 t10

B
t0 t1

A
B X

Y
Z F
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Timing Diagram Example

A
Y X Z t2 t3 t4 t5 t6 t7 t8 t9 t10

B
t0 t1

A
B

A 0 1 0 1

B 1 1 0 0

F 1 0 0 1
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F = A B

Combinational Logic
N inputs
Combinational circuits M outputs

Outputs, at any time, are determined by the input combination We will discuss Multiplexers / De-Multiplexers Decoders / Encoders Comparators Parity Checkers / Generators Binary Adders / Subtractors Integer Multipliers
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Multiplexers (Mux)
Functionality: Selection of a particular input Route 1 of N inputs N (A) to the output F log 2 Require selection bits (S) En(able) bit can disable the route and set F to 0

A0 A1 A2 A3

En

4-to-1 Mux
S1 S0

Multiplexers (Mux) w/out Enable

S1 S0 0
1 0 1 0 1 0

A3 X
X X 0 X X X

A2 X
X 0 X X X 1

A1 X
0 X X X 1 X

A0 0
X X X 1 X X

F 0
0 0 0 1 1 1

A0 A1 A2 A3

0
0

4-to-1 Mux
S1 S0

1 1 0 0 1

Multiplexers (Mux) w/out Enable

A0 A1 A2 A3

S1 0

S0 0 1 0

F A0 A1 A2

4-to-1 Mux
S1 S0

0 1

A3

F S1S0A0 S1S0A1 S1S0A2 S1S0A3

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Logic Diagram of a 4-to-1 Mux

F S1S0A0 S1S0A1 S1S0A2 S1S0A3
S1 S0 A0 F

A1

A2

A3

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Multiplexers (Mux) w/ Enable

A0 A1 A2 A3

En

En 0

S1 X 0 0 1 1

S0 X 0 1 0 1

F 0 A0 A1 A2 A3

4-to-1 Mux
S1 S0

1 1 1 1

F En (S1S0A0 S1S0A1 S1S0A2 S1S0A3) EnS1S0A0 EnS1S0A1 EnS1S0A2 EnS1S0A3

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4-to-1 Mux w/ Enable Logic

F En (S1S0A0 S1S0A1 S1S0A2 S1S0A3)
S1 S0 A0 F

A1

A2

A3 En
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4-to-1 Mux w/ Enable Logic

F En S1S0A0 En S1S0A1 EnS 1S0A2 EnS 1S0A3
S1 S0 A0 F

A1

A2

Reduce one Gate Delay by using 4-input AND gate for the 2nd level

A3 En
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4-to-1 Mux using Transmission Gates

S1 S0 A0 S1 0 S0 0 1 0 1 F A0 A1 A2 A3

A1

1 1

A2

A3

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4-to-1 Mux using Transmission Gates

S1 S0=0 A0 S1 0 S0 0 1 0 1 F A0 A1 A2 A3

A1

1 1

A2

A3

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4-to-1 Mux using Transmission Gates

S1=0 S0=0 A0 A0 S1 0 0 S0 0 1 0 1 F A0 A1 A2 A3

A1

1 1

A2 A2 A3

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4-to-1 Mux using Transmission Gates

S1 S0=1 A0 S1 0 S0 0 1 0 1 F A0 A1 A2 A3

A1

1 1

A2

A3

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4-to-1 Mux using Transmission Gates

S1=1 S0=1 A0 A1 S1 0 0 S0 0 1 0 1 F A0 A1 A2 A3

A1

1 1

A2 A3 A3

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4-to-1 Mux using Transmission Gates with Enable (F=0 when En=0)
En S1=1 S0=1 A0

En S1 S0 A1
0 1 A2 F A3 X 0 X 0

F
0 A0

1
1 1

0
1 1

1
0 1

A1
A2 A3

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4-to-1 Mux using Transmission Gates with Enable (F=Z when En=0)

A0 X Y En 0 1 En=1 En=0 X=S0 Y=S0 X=0 Y=1 (To disable both TG) 1 1 1 S1 X 0 0 1 1 S0 X 0 1 0 1 F Z A0 A1 A2 A3

A1

X=En S0
Y=En + EnS0 = En + S0

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4-to-1 Mux using Transmission Gates with Enable (F=Z when En=0)
X=En S0 S0 En A0 X Y En 0 1 1 1 1 S1 X 0 0 1 1 S0 X 0 1 0 1 F Z A0 A1 A2 A3 Y=En + EnS0 = En + S0

A1

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4-to-1 Mux using Transmission Gates with Enable (F=Z when En=0)
X=En S0 S0 En A0 En A1 0 1 1 1 1 A3 S1 X 0 0 1 1 S0 X 0 1 0 1 F Z A0 A1 A2 A3 Y=En + EnS0 = En + S0

A2

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4-to-1 Mux using Transmission Gates with Enable (F=Z when En=0)
S1 S0 En A0 F A1
En S1 X 0 0 1 1 S0 X 0 1 0 1 F Z A0 A1 A2 A3 0 1 1

A2

A3

1 1

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Simplified 4-to-1 Mux using TGs with Enable (F=Z when En=0)
En S1 S0 A0 X Y F X=En S0 Y=En + EnS0 = En + S0

A1
En S1 X 0 0 1 1 S0 X 0 1 0 1 F Z A0 A1 A2 A3

A2

0 1 1

A3

Only Disable the 2nd level

1 1

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Quadruple 2-to-1 Line Mux

En A[3:0] A3..0 2-to-1

B[3:0]

B3..0

Mux (4-bit bus)

SEL

F[3:0]

En 0 1 1

SEL X 0 1

F[3:0] 0000 A[3:0] B[3:0]

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Quadruple 2-to-1 Line Mux

A0 A1 A2 A3 F0 F1 F2 F3
En 0 1 1 SEL X 0 1 F[3:0] 0000 A[3:0] B[3:0]

Fx=AxEnSEL+BxEnSEL

SEL B0

B1
B2 B3 En

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Design Canonical Form w/ MUX

F(A, B, C) A BC ABC ABC ABC

F(A, B, C) m(1, 2, 6, 7)
0
1 1 0 0 0 1 1 A0 A1 A2 A3 A4 A5 A6 A7

Each input in a MUX is a minterm

8-to-1 Mux

S2 S1 S0

A B C
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Design Canonical Form w/ MUX

F(A, B, C) m(1, 2, 6, 7)

F ABC ABC ABC ABC

A
0 0 1 1

B
0 1 0 1

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Design Canonical Form w/ MUX

F m(1, 2, 6, 7)

F ABC ABC ABC ABC

A
0
F

C C 0

A0 A1 A2 A3

En

B
0 1 0 1

F
C C 0 1

4-to-1 Mux
S1 A S0 B

0 1 1

1
Vdd

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Design Canonical Form w/ MUX

F m(1, 2, 6, 7)

F ABC ABC ABC ABC

B
0 0 1 1

C
0 1 0 1

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Design Canonical Form w/ MUX

F m(1, 2, 6, 7)

F ABC ABC ABC ABC

B
0
F

A0 A
Vdd

En

C
0 1 0 1

F
0 A 1 A

A1 A2 A3

4-to-1 Mux
S1 B S0 C

0 1 1

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Demultiplexers (DeMux)

A0 A1 A2 A3

D0

4-to-1 Mux
S1 S0

1-to-4 DeMux D2
S1 S0
D3

D1

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DeMux Operations
S1 0 0 D0 A 1 1 D1 S0 0 1 0 1 D3 0 0 0 A D2 0 0 A 0 D1 0 A 0 0 D0 A 0 0 0

1-to-4 DeMux D2
S1 S0
D3

D 0 S1 S0 A D1 S1S0 A D 2 S1 S0 A D 3 S1S0 A
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DeMux Operations
S1
S1 D0 S0 D1

S0 0 1 0 1

D3 0 0 0 A

D2 0 0 A 0

D1 0 A 0 0

D0 A 0 0 0

0 0 1 1

D2

D 0 S1 S0 A D1 S1S0 A D 2 S1 S0 A D 3 S1S0 A
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D3

DeMux Operations w/ Enable

S1 D0

S0
D1 En 0 D2 1 1 D3 1 1 S1 X 0 0 1 1 S0 X 0 1 0 1 D3 D2 0 0 0 0 A 0 0 0 A 0 D1 0 0 A 0 0 D0 0 A 0 0 0

En

A
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